FAQ

When running a design using AIL, such as a SPI4.2 design, in ispLEVER using an LatticeSC/M device, why do I get an error in MAP? ERROR - map: Delay cell rxgb/genblk1_u_15__CDLY has an invalid FDEL setting - when the delay cell is in CFGBIT (static) mode, and the IOLOGIC AIL is on, the valid FDEL value range is from 8 to 39.

Due to a hardware limitation, the valid range for the FDEL attribute that uses AIL is between 8 - 39. Thhis error message informs the customer that the FDEL value of the AIL component is outside of this valid FDEL range.

If you have an old SPI4.2 core or IDDR / DELAY element that was generated, then you may run into this error. This can be fixed by generating a new element, updating your IP core, or manually changing the HDL FDEL attribute to have a value that's between 8 and 39.

This was fixed for ispLEVER 7.2 and above. Any IP core or components using AIL prior to this software update may have an invalid FDEL Range. If you are outside of the valid range, the AIL circuit will still work. The software was updated to reflect the true range.