IDE/ATA Interface Controller

Related Products

Reference Design LogoThis reference design implements a generic IDE interface controllercompliant with the ATA/ATAPI-5 Standard. It is also a WISHBONE-compliant host controller that provides a simpleinterface to low-cost, non-volatile memories such as hard disk drives, CD-ROM players/writers and CompactFlashand PC card devices. This document and the design are based on the OpenCores ATA/ATAPI-5 core.

Features

  • ATA/ATAPI Revision 5 compliant design
  • Common PIO (Programmed Input Output) compatible timing setting for all connected devices
  • Fast PIO dataport timing settings for connected devices
  • Single-word/multi-word timing settings for connected devices
  • PIO mode that supports PINGPONG read and write
  • Automatic big endian versus little endian conversion
  • DMA read and write buffer
  • WISHBONE DMA engine compatible
  • WISHBONE Revsion B2 compliant
  • 32-bit host interface
  • Operation in a wide range of input clock frequencies

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Block Diagram

IDE/ATA Interface Controller

Performance and Size

Tested Devices* Performance I/O Pins Design Size Revision
LCMXO2280C-5FT324C >100MHz 194 752 LUTs 1.0

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise. 

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
IDE/ATA Interface Controller - WISHBONE Compatible - Source Code
RD1095 1.0 6/28/2010 ZIP 756.3 KB
IDE/ATA Interface Controller - WISHBONE Compatible - Documentation
RD1095 1.0 6/28/2010 PDF 769.8 KB

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