UART 16550 Transceiver

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Reference Design LogoThe Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel conversion on data characters received from a peripheral device or a modem, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, framing, or break interrupt).

The UART has complete modem-control capability, and a processor-interrupt system. Interrupts can be programmed to the user’s requirements, minimizing the computing required to handle the communications link. The register set and data transfer protocol of this design is compatible with the National Semiconductor PC16550D UART.

This reference design is implemented in Verilog. The Lattice iCEcube2™ Place and Route tool integrated with the Synplify Pro synthesis tool is used for implementation of the design. The design uses an iCE40™ ultra low density FPGA and can be targeted to other iCE40 family members.


  • Compatible with National Semiconductor PC16550D UART
  • Configurable data widths of 5, 6, 7 or 8 bits
  • Configurable stop bits – 1, 1.5 or 2 bits for transmit operations
  • Even parity, odd parity or stick parity configuration for transmit and receive operations
  • Programmable divisor latch for custom baud rates
  • Interrupt generation logic with readable Interrupt Identification Register
  • Verilog RTL, test bench and Aldec A-HDL script for simulationCompatible with digitizer chip (TSC2046)

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Block Diagram

UART 16550 Transceiver

Performance and Size

Device Family Utilization (LUTs) Language fMAX (MHz) I/O Pins Architectural Resources
iCE40™ 622 Verilog >100 29 N/A

Performance and resource utilization characteristics are generated using iCE-40LP1K-CM121 with iCEcube2 design software.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


Technical Resources
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UART 16550 Transceiver - Documentation
RD1138 1.0 10/12/2012 PDF 1.5 MB
UART 16550 Transceiver - Source Code
RD1138 1.1 1/12/2015 ZIP 741 KB

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