BSCAN - Multiple Port Linker (BSCAN2)

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Reference Design LogoAccording to the IEEE 1149.1 Boundary Scan System, every complex system can have more than one boundary-scan-compliant scan port. If each of these scan ports are linked together, then the chances of enhancing the scan capability would definitely increase. In this design, the multiple scan ports are linked together by implementing instructions feed in to the IEEE 1149.1 port. The MSP (Multiple Scan Port) device can be used to link the four local scan ports or it can be completely bypassed. An ENABLE signal is provided, when low, the device outputs are tri-stated so a Lattice ispDOWNLOAD® Cable can be used directly on the secondary chains for in-system programming.

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Block Diagram

BSCAN - Multiple Port Linker (BSCAN2)

Performance and Size

Device Family Tested Devices* Performance I/O Pins Utilization Revision
4-Port Implementation
MachXO2™ 1 LCMXO2-256HC-
4TG100C		 >30MHz 30 88 LUTs (Verilog Source)
85 LUTs (VHDL Source)		 4.6
MachXO™ 2 LCMXO256C-5T100C >30MHz 30 88 LUTs (Verilog Source)
85 LUTs (VHDL Source)		 4.6
LatticeXP2™ 3 LFXP2-5E-5M132C >30MHz 30 83 LUTs (Verilog Source)
84 LUTs (VHDL Source)		 4.6
ispMACH® 4000ZE™ 4 LC4128ZE-5TN100C >30MHz 30 60 Macrocells
(Verilog/VHDL Source)		 4.6
ispMACH® 4000V/B/C/Z™ 5 LC4128V-27T100C >30MHz 30 60 Macrocells
(Verilog/VHDL Source)		 4.6
Platform Manager™ 6 LPTM10-1247-
3TG128CES		 >30MHz 30 88 LUTs (Verilog Source)
85 LUTs (VHDL Source)		 4.6
ECP5™ 7 LFE5UM-85F-
CABGA756		 >30MHz 30 88 LUTs (Verilog Source)
85 LUTs (VHDL Source)		 4.6
8-Port Asset Implementation
MachXO2™ 1 LCMXO2-256HC-
4TG100C		 >30MHz 50 129 LUTs (Verilog Source)
122 LUTs (VHDL Source)		 4.6
MachXO™ 2 LCMXO256C-5T100C >30MHz 50 219 LUTs (Verilog Source)
212 LUTs (VHDL Source)		 4.6
LatticeXP2™ 3 LFXP2-5E-5M132C >30MHz 50 108 LUTs (Verilog Source)
122 LUTs (VHDL Source)		 4.6
ispMACH® 4000ZE™ 4 LC4128ZE-5TN100C >30MHz 50 108 Macrocells
(Verilog/VHDL Source)		 4.6
ispMACH® 4000V/B/C/Z™ 5 LC4128V-27T100C >30MHZ 50 108 Macrocells
(Verilog/VHDL Source)		 4.6
Platform Manager™ 8 LPTM10-12107-
3FTG208CES		 >30MHz 50 129 LUTs (Verilog Source)
122 LUTs (VHDL Source)		 4.6
ECP5™ 7 LFE5UM-85F-
CABGA756		 >30MHz 50 129 LUTs (Verilog Source)
122 LUTs (VHDL Source)		 4.6
8-Port JTAG Implementation
MachXO2™ 1 LCMXO2-640HC-
4TG100C		 >30MHz 50 154 LUTs (Verilog Source)
147 LUTs (VHDL Source)		 4.6
MachXO™ 2 LCMXO640C-5T100C >30MHz 50 271 LUTs (Verilog Source)
147 LUTs (VHDL Source)		 4.6
LatticeXP2™ 3 LFXP2-5E-
5M132C		 >30MHz 50 148 LUTs (Verilog Source)
149 LUTs (VHDL Source)		 4.6
ispMACH® 4000ZE™ 4 LC4128ZE-5TN100C >30MHz 50 127 Macrocells
(Verilog/VHDL Source)		 4.6
ispMACH® 4000V/B/C/Z™ 5 LC4128V-27T100C >30MHz 50 127 Macrocells
(Verilog/VHDL Source)		 4.6
Platform Manager™ 6 LPTM10-12107-
3FTG208CES		 >30MHz 50 154 LUTs (Verilog Source)
147 LUTs (VHDL Source)		 4.6
ECP5™ 7 LFE5UM-85F-
CABGA756		 >30MHz 50 193 LUTs (Verilog Source)
195 LUTs (VHDL Source)		 4.6

1. Performance and utilization characteristics are generated using LCMX02-640HC-4TG100C with Lattice Diamond® 3.1 design software with LSE (Lattice Synthesis Engine).
2. Performance and utilization characteristics are generated using LCMXO2640C-5T100C with Diamond 3.1 design software.
3. Performance and utilization characteristics are generated using LFXP2-5E-5M132C with Lattice Diamond 3.1 design software.
4. Performance and utilization characteristics are generated using LC4128ZE-5TN100C with ispLEVER® Classic 1.4 software.
5. Performance and utilization characteristics are generated using LC4128V-27T100C with ispLEVER Classic 1.4 software.
6. Performance and utilization characteristics are generated using LPTM10-12107-3FTG208CES with ispLEVER 8.1 SP1 software.
7. Performance and utilization characteristics are generated using LFE5UM-85F-CABGA756 with Lattice Diamond 3.1 design software with LSE.

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise. 

Documentation

Quick Reference
Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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Using Multiple Boundary Scan Port Linker (BSCAN2)
FPGA-AN-02017 1.1 1/9/2022 PDF 774.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Using Multiple Boundary Scan Port Linker (BSCAN2)
FPGA-AN-02017 1.1 1/9/2022 PDF 774.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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BSCAN2 - Multiple Scan Port Linker - Documentation
FPGA-RD-02106 4.9 1/29/2021 PDF 918.1 KB
BSCAN2 - Multiple Boundary Scan Port Linker - Source Code
RD1002 4.6 3/13/2014 ZIP 2.6 MB

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