32 Bit PCI Master/Target


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Peripheral Component Interconnect (PCI) is a widely accepted bus standard that is used in many applications including telecommunications, embedded systems, high performance peripheral cards, and networking.

Lattice's PCI IP core provides an ideal solution that meets the needs of today's high performance PCI applications. It is fully compliant with the PCI Local Bus Specification, revision 2.2 for speeds up to 66MHz. The PCI core provides a customizable 32/64-bit master/target or target solution. The core bridges the gap between the PCI interface and a specific design application, providing an integrated PCI solution. The PCI solution allows designers to focus on the application rather than on the PCI specification, resulting in a faster time-to-market.

The Lattice PCI offering is available in a number of configurations covering 32-bit PCI, 64-bit PCI, 32-bit local bus, 64-bit local bus, master/target and target applications. In this document, details of 64-bit operation and master operation only apply when relevant. The appendix to the user's guide shows what cores are available on which devices.

Features

  • Available as 32/64-Bit PCI Bus and 32/64-Bit Local Bus
  • PCI SIG Local Bus Specification, Revision 3.0 Compliant
  • 64-Bit Addressing Support (Dual Address Cycle)
  • Capabilities List Pointer Support
  • Parity Error Detection
  • Up to Six Base Address Registers (BARs)
  • Fast Back-to-Back Transaction Support
  • Supports Zero Wait State Transactions
  • Special Cycle Transaction Support
  • Customizable Configuration Space
  • Up to 66MHz PCI
  • Fully Synchronous Design

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Block Diagram

32 Bit PCI Master/Target

Performance and Size

LatticeECP31
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins		 fMAX (MHz)
32-bit Master/Target 33 MHz 683 1059 640 - 50 33
32-bit Master/Target 66 MHz 1076 1691 661 - 50 66

1. Performance and utilization data are generated using an LFE3-95EA-7FN1156CES device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.

LatticeECP2M1
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins		 fMAX (MHz)
32-bit Master/Target 33 MHz 856 1068 642 - 50 33
32-bit Master/Target 66 MHz 1086 1700 663 - 50 66

1. Performance and utilization data are generated using an LFE2M-35E-6F672C device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M family.

LatticeECP21
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins		 fMAX (MHz)
32-bit Master/Target 33 MHz 856 1068 642 - 50 33
32-bit Master/Target 66 MHz 1086 1700 663 - 50 66

1. Performance and utilization data are generated using an LFE2-20E-6F672C device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2 family.

LatticeEC/P1
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins		 fMAX (MHz)
32-bit Master/Target 33 MHz 846 1060 642 - 50 33
32-bit Master/Target 66 MHz 1083 1690 663 - 50 66

1. Performance and utilization data are generated using an LFEC33E-5F672C device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP/EC family.

LatticeSC1
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins		 fMAX (MHz)
32-bit Master/Target 33 MHz 724 1050 640 - 50 33
32-bit Master/Target 66 MHz 1085 1722 663 - 50 66

1. Performance and utilization data are generated using an LFSC3GA25E-6F900C device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeSC family.

MachXO21
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins		 fMAX (MHz)
32-bit Master/Target 33 MHz 406 803 582 - 50 33

1. Preliminary information. Performance and utilization data are generated using an LCMXO2-1200HC-6TG144CES device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the MachXO2 family.

MachXO1
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins		 fMAX (MHz)
32-bit Master/Target 33 MHz 542 1060 642 - 50 33

1. Performance and utilization data are generated using an LCMXO2280C-5FT324C device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the MachXO family.

LatticeXP21
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins		 fMAX (MHz)
32-bit Master/Target 33 MHz 851 1060 640 - 50 33
32-bit Master/Target 66 MHz 1081 1692 661 - 50 66

1. Performance and utilization data are generated using an LFXP2-17E-6F484C device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family.

LatticeXP1
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins		 fMAX (MHz)
32-bit Master/Target 33 MHz 846 1060 642 - 50 33
32-bit Master/Target 66 MHz 1083 1690 663 - 50 66

1. Performance and utilization data are generated using an LFXP20C-5F484C device with Lattice Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP family

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
MachXO2 PCI-MT32-M2-UT1 PCI-MT32-M2-US
MachXO PCI-MT32-XO-UT6 -
LatticeECP3 PCI-MT32-E3-UT6 PCI-MT32-E3-US
LatticeECP2M PCI-MT32-PM-UT6 -
LatticeECP2 PCI-MT32-P2-UT6 -
LatticeEC/ECP PCI-MT32-E2-UT6 -
LatticeSC/M PCI-MT32-SC-UT6 -
LatticeXP2 PCI-MT32-X2-UT6 -
LatticeXP PCI-MT32-XM-UT6 -

IP Version: PCI Master/Target 33MHz = 6.6, PCI Master/Target 66MHz = 6.4

Evaluate: To download a full evaluation version of this IP, go to the Lattice IP Server tab in the IPexpress Main Window. All ispLeverCORE IP cores and modules available for download are visible on this tab. *PCI cores for ORCA and ispXPGA,devices are supported by the Lattice factory-configurable design flow.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
PCI IP Core User's Guide
PCI Core User Guide for LatticeSC, LatticeECP3, LatticeECP2/M, LatticeECP/EC, LatticeXP, Mach XO, and MachXO2 		IPUG18 9.2 11/8/2010 PDF 4.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
IP Module Evaluation Tutorial
8/1/2004 PDF 216.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Evaluation Package for 32 Bit PCI Master/Target for ORCA 4
10/1/2003 ZIP 1.2 MB
Evaluation Package for PCI Master/Target 32-bit / 33MHz for LatticeSC
2/21/2006 ZIP 672.7 KB
Evaluation Package for PCI Master/Target 32-bit / 33MHz for LatticeECP/EC
2/1/2005 ZIP 808.7 KB
Evaluation Package for PCI Master Target 32 bit for LatticeXP - Configuration 2
8/1/2005 ZIP 1.1 MB
Evaluation Package for PCI Master/Target 32-bit / 66MHz for LatticeSC
2/21/2006 ZIP 1 MB
Evaluation Package for 32 Bit PCI Master/Target for MachXO
12/1/2005 ZIP 649.8 KB
Evaluation Package for 32 Bit PCI Master/Target for ispXPGA
9/1/2003 ZIP 2.2 MB
Evaluation Package for PCI Master/Target 32-bit / 33MHz for LatticeXP
5/1/2005 ZIP 658.3 KB
Evaluation Package for PCI Master Target 32 for ECP/EC Configuration 2
8/1/2005 ZIP 1 MB
Evaluation Package for 32 Bit PCI Master/Target for ORCA 4 - Configuration 2
11/1/2003 ZIP 2.2 MB

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