10Gb Ethernet MAC IP Core

Transmits and Receives Data Between a Host Processor and an Ethernet Network

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The Lattice Semiconductor 10 Gb Ethernet MAC IP Core supports the ability to transmit and receive data between a host processor and an Ethernet network. The main function of the 10 Gb Ethernet MAC is to ensure that the Media Access rules specified in the 802.3 IEEE standards are met while transmitting a frame of data over Ethernet. On the receive side, the Ethernet MAC extracts the different components of a frame and transfers them to higher applications through an AXI4-stream interface.

Transmit MAC - The Transmit MAC is responsible for controlling access to the physical medium. This feature is useful if the frames being presented for transmission already contain the FCS field.

Dynamic Speed Selection - This module converts between XGMII, GMII and MII interfaces. This is enabled when Dynamic Speed Selection attribute is enabled or if PHY interface is set to any of the following: 8-bit GMII, 16-bit GMII or MII.

Features

  • Supports standard 10 Gbps Ethernet link layer data rate
  • 64-bit wide internal data path operating at 156.25 MHz
  • AXI4-stream interface on Client transmit and receive interfaces
  • Supports Deficit Idle Count
  • Supports VLAN, Jumbo Frames and WAN mode

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Block Diagram

10Gb+ Ethernet MAC IP Core Block DiagramExpand Image

Resource Utilization

ECP51,2
Mode SLICEs LUTs Registers sysMEM EBRs fMAX (MHz)
Multicast Address Filtering 2796 4085 2696 4 152.25

1. Performance and utilization data are generated using an LFE5UM-85F-8FBG756CES device with Lattice’s Diamond 3.4. Performance may vary when using a different software version or targeting a different device density or speed grade within the ECP5 family.
2. The 10 Gb Ethernet MAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O Buffers integrated in the ECP5 series FPGA. Thus the application implementing the 10 Gb Ethernet MAC will utilize I/O pins.

LatticeECP31,2
Mode SLICEs LUTs Registers sysMEM EBRs fMAX (MHz)
Multicast Address Filtering 3190 4681 2814 4 156.25

1. Performance and utilization data are generated using an LFE3-150EA-8FN1156C device with Lattice’s Diamond 3.4. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.
2. The 10 Gb Ethernet MAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O Buffers integrated in the LatticeECP3 series FPGA. Thus the application implementing the 10 Gb Ethernet MAC will utilize I/O pins.

LatticeECP2M/S1,2
Mode SLICEs LUTs Registers sysMEM EBRs fMAX (MHz)
Multicast Address Filtering 3153 4370 2777 4 181

1. Performance and utilization data are generated using an LFE2M35E-7F672C device with Lattice’s Diamond 1.1 software with Synplify Pro D-2010.03L-SP1 synthesis. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M/S family.
2. The 10 Gb+ Ethernet MAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O Buffers integrated in the LatticeECP2M series FPGA. Thus the application implementing the 10 Gb+ Ethernet MAC specification will utilize I/O pins.

LatticeECP2/S1,2
Mode SLICEs LUTs Registers sysMEM EBRs fMAX (MHz)
Multicast Address Filtering 3153 4022 2777 4 170

1. Performance and utilization data are generated using an LFE2-35E-7F672C device with Lattice’s Diamond 1.1 software with Synplify Pro D-2010.03L-SP1 synthesis. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2/S family.
2. The 10 Gb+ Ethernet MAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O Buffers integrated in the LatticeECP2 series FPGA. Thus the application implementing the 10 Gb+ Ethernet MAC specification will utilize I/O pins.

LatticeSC/M1,2
Mode SLICEs LUTs Registers sysMEM EBRs fMAX (MHz)
Multicast Address Filtering 2961 4370 2764 4 205

1. Performance and utilization data are generated using an LFSC3GA25E-5F900C device with Lattice’s Diamond 1.1 software with Synplify Pro D-2010.03L-SP1 synthesis. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeSC family.
2. The 10 Gb+ Ethernet MAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O Buffers integrated in the LatticeSC series FPGA. Thus the application implementing the 10 Gb+ Ethernet MAC specification will utilize I/O pins.

Ordering Information

Device Family Part Number
Multi-site Perpetual Single Machine Annual
ECP5 ETHER-10G-E5-UT ETHER-10G-E5-US
LatticeECP3 ETHER-10G-E3-UT4 ETHER-10G-E3-US
LatticeECP2 ETHER-10G-P2-UT4 -
LatticeECP2M ETHER-10G-PM-UT4 -
LatticeSC/M ETHER-10G-SC-UT4 -

IP Version: 4.3

Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LatticeECP3 and Marvell 10 Gbps Physical/MAC Layer Interoperability
TN1219 1.0 7/26/2010 PDF 1.4 MB
LatticeECP3 and Broadcom 10 Gbps Physical/MAC Layer Interoperability
TN1218 1.1 2/13/2012 PDF 3.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LatticeECP3 and Marvell 10 Gbps Physical/MAC Layer Interoperability
TN1219 1.0 7/26/2010 PDF 1.4 MB
LatticeECP3 and Broadcom 10 Gbps Physical/MAC Layer Interoperability
TN1218 1.1 2/13/2012 PDF 3.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
10Gb+ Ethernet MAC User Guide
10Gb Ethernet MAC 		IPUG39 02.9 12/28/2010 PDF 864.1 KB
LatticeECP3 and ECP5 10Gb Ethernet MAC IP Core UserGuide
10GB Ethernet MAC 		IPUG114 1.0 4/24/2015 PDF 4.2 MB
10 Gb Ethernet MAC IP Core - Lattice Radiant Software
FPGA-IPUG-02162 1.1 12/1/2021 PDF 1.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB

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