Dedicated DDR Memory Interface Circuitry

Designers of cost sensitive equipment naturally select the memory technology that provides the lowest cost per bit given their technical requirements; traditionally, this has often meant Synchronous DRAM (SDRAM). However, in the last few years volume shipments of Double Data Rate DRAM have been growing to the point where DDR DRAM is expected to represent over 50% of the bits shipped in 2004. Increasingly, designers are finding that DDR DRAM provides a lower cost per bit than SDRAM.

DDR Design Challenges

Although DDR DRAM in many cases provides cheaper storage, it is significantly more difficult to interface to than SDRAM.

The design challenges include aligning data (DQ) with data strobe (DQS) signals, splitting a stream of data with transitions on both edges of the clock into multiple streams transitioning on one edge of the clock, and managing data transfer from the DQS clock domain to the system clock domain. The alignment of DQ and DQS is made all the more challenging by the bi-directional nature of the DQS signal.

LatticeXP FPGA Devices Simplify DDR Memory Interface

LatticeXP FPGA devices provide dedicated resources to align DQ and DQS signals, multiplex to and from double data rate, and transfer data from the DQS clock domain to the system clock domain. The approach taken by LatticeXP FPGA devices contrasts with other low-cost FPGAs that provide either no DDR support or only limited support. The impact can be dramatic; through dedicated DDR support resources LatticeXP FPGA devices save, for general-purpose use, between 500 and 1000 registers when implementing a 64-bit wide memory interface. This represents a considerable portion of the 1.5K general-purpose registers in the smallest devices. Performance is also improved by 25% over other low-cost FPGAs, allowing faster operation, more margin to specifications or the use of a slower speed grade device.