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LatticeSCM Memory Controllers

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Memory devices are ubiquitous in systems today. As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. Current memory interfaces often require clock speeds in the excess of 200 MHz to achieve the throughput requirements of line and switch cards. As a result, these next generation memory interfaces are also increasingly challenging to design to.

Implementing high-speed, high-efficiency memory interfaces in programmable logic devices like FPGAs has always been a major challenge for designers. Lattice Semiconductor Corporation offers customers complete high-speed memory interface solutions in the high-speed, high-performance FPGA family, the LatticeSCM. The LatticeSCM family implements full-featured embedded high-speed memory controllers on-chip to interface smoothly to the next generation high-speed, high performance DDR SDRAM, QDR SRAM, and RLDRAM memory devices. These high-speed memory controllers are implemented using ASIC (MACO) technology. Up to two independent memory controllers are available in the LatticeSCM family of devices. The embedded memory controllers coupled with the high-speed I/O structures, clock management resources, and the high-speed FPGA fabric significantly reduce design risk and time-to-market for the next generation memory based designs. The full-featured, fully tested controllers provide customers a low-risk time-to-market solution for high-speed memory interfaces.

LatticeSCM MACO Memory Controller Block

LatticeSCM MACO Memory Controller Block

LatticeSCM Memory Controllers Support
Memory Type Application LatticeSCM Support
DDR SDRAM Large buffer memories 200 MHz 400 Mbps
DDR II SDRAM Higher bandwidth large buffer memories 333 MHz 667 Mbps
QDR I/II SRAM Low latency applications 300 MHz 600 Mbps
RLDRAM I/II Low latency, fast random access 400 MHz 800 Mbps
LatticeSCM DDR I/II Memory Controllers:

  • Interfaces to industry standard DDR I/DDR II SDRAM
  • Supports SDRAM data path widths of 8-72 bits
  • Varying address widths for different memory devices
  • Programmable burst length of 4 or 8
  • Posted CAS functionality
  • Programmable CAS latency of 3 or higher
  • Intelligent bank management to minimize ACTIVE commands
  • Command pipeline to maximize throughput
  • Programmable timing parameters
  • DDR I SDRAM frequency of 200 MHz (400 Mbps)
  • DDR II SDRAM frequency of 333 MHz (667 Mbps) 
  • Byte level writing through Data Mask signals
  • ODT signal generation
  • On-chip termination used, including special mode for DDR II 
  • Supports both true and complementary DQS during write.


LatticeSCM QDR I/II Memory Controllers:

  • Interfaces to industry standard QDR I/II SRAM
  • Configurable data and address widths to be able to address memory devices of various sizes
  • Supports Programmable burst sizes
  • Supports interleaving of read and write accesses as required by QDR II memory
  • Proven controller from current FPSC device: ORSPI4
  • Supports clock frequency up to 300 MHz (600 Mbps).


LatticeSCM RLDRM I/II Memory Controllers:

  • Supports both RLDRAM I and II Memory devices
  • Supports both CIO and SIO RLDRAM II devices
  • Programmable burst lengths of 2, 4 or 8
  • Supports two chip selects to enable cascading two or more RLDRAM devices 
  • Programmable refresh counter
  • Cyclic bank access to maximize data bandwidth
  • Supports the following commands at the user interface: READ, WRITE, Mode Register Set (MRS)
  • Command pipeline to maximize throughput
  • Supports data path widths of 16 and 32 for RLDRAM-I and 9, 18 and 36 bits for RLDRAM-II CIO and 9, 18 bits for RLDRAM-II SIO
  • Supports data mask bits
  • Speeds of 300 MHz (600 Mbps) for RLDRAM-I and 400 MHz (800 Mbps) for RLDRAM-II memory devices.