HSPICE Models for FPGA Devices

HSPICE models of high-speed I/O, including SERDES (if applicable), are available for the FPGA device families listed below. Due to specific license requirements, the models are available on request only.

HSPICE I/O Kit for LatticeSC and ORCA Series 4 FPSC Devices

For LatticeSC and ORCA Series 4 FPSC devices (ORT82G5, ORSO82G5, OST42G5, ORSO42G5 and ORSPI4). Includes a variety of package, connector, and PCB trace models.

HSPICE I/O Kit for LatticeECP, LatticeECP2M and LatticeECP3

• Full silicon process models (HSPICE encrypted)
• IO and SERDES circuit models, input and output only (HSPICE encrytped)
• Fuse vector files for changing the IO type and current setting during simulation (both single ended and differential fuse vector files)
• Does not include package models
• Top level test benches and results plots in BMP for LVDS output, LVDS input, SERDES output, SERDES input, SERDES output to input, and Single Ended LVCMOS/SSTL/HSTL
• Documentation is included with the kit. This describes what is simulated and includes brief examples of how to run an HSPICE simulation on UNIX or Windows operating systems. There is also additional information about corrections to the files between versions. The HSPICE models do receive periodic updates, so it is recommended to request the latest HSPICE IO Kit prior to new simulation efforts.
   

A license agreement is required for all HSPICE models.

• Request an HSPICE I/O Kit