Expanded In-System Programmability (ispXP)

Lattice's ispXP^TM (eXpanded Programmability) technology combines the best features of non-volatile (E² or Flash) and SRAM technologies. ispXP utilizes a combination of non-volatile (E²PROM or Flash) cells and SRAM technology to deliver a single-chip solution supporting "instant-on" start-up and infinite reconfigurability. A non-volatile E² or Flash array distributed within an ispXP device stores the device configuration. At power-up this information is transferred in a massively parallel fashion into SRAM bits that control the operation of the device. ispXP technology is available in the LatticeXP^TMand ispXPGA^TM families of FPGAs, the ispXPLD^TM family of XPLDs, and the MachXO^TM family of crossover logic.

Features and Benefits

• Instant-on at Power-up
  • With non-volatile memory the PLD Logic is available in 1mS of power-up
  • PLD logic available before microprocessor reset release
  • Superior solution for microprocessor glue logic and decoder logic
  • Supports power-up control applications
• High Security - Eliminates External Configuration Bitstream
  • Excellent for military and security-sensitive applications
  • Non-volatile security bits protect PLD/FPGA pattern
• Single-Chip Solution Eliminates Need for Boot PROM or External Storage Device
  • Simplified design process
  • Reduced board space
  • Reduced inventory, handling and manufacturing costs
  • Improved reliability
• Available in Three High-Performance Families Supporting 1.2, 1.8, 2.5 or 3.3V Power Supplies
  • LatticeXP and ispXPGA Family of FPGAs
  • ispXPLD Family of XPLDs
  • MachXO Family of crossover logic
• Infinitely Reconfigurable SRAM via IEEE 1532 or sysCONFIG^TM (Microprocessor) Interface
• In-System Programmable E²PROM or Flash memories via IEEE 1532 Port and sysConfig port (LatticeXP only)
• Boundary Scan Testable via IEEE 1149.1 (JTAG) Port

Flexible Programming and Configuration

• Instant-on (less than <1mS)
• Reliable configuration by design
• Reprogram Non-volatile in background while running logic from SRAM (Real time reprogrammable)

Configuration in LatticeXP devices

High Security

• ispXP devices include security scheme to prevent readback
• No external bitstream - totally secure from bitstream "snooping"
• Excellent solution for security-sensitive applications

Single Chip Solution

• No external Boot PROM needed for configuration
  • No Boot PROM noise issues
  • No Boot PROM reliability issues
  • No Boot PROM board space concerns
• Single-chip solution reduces inventory, handling, and manufacturing costs
• Simplified design