SERDES

Serializer-DeSerializer

LatticeECP2M devices feature up to 16 channels of industry’s lowest cost embedded SERDES. The SERDES block is a cost-efficient digital CDR implementation that has been architected to specifically support popular 8b/10b based packet protocols that are primarily used in serial chip to chip and small form-factor backplane applications.

Each SERDES channel contains dedicated transmit and receive circuitry for high-speed full-duplex serial data transfers at data rates up to 3.125 Gbps. The corresponding Physical Coding Sublayer (PCS) includes base synchronization state machines, 8b/10b encoding/decoding and rate matching circuitry.

The PCS also provides bypass modes that allow a direct 8 or 10-bit interface from the SERDES to the FPGA logic.

At costs that are a fraction of premium SERDES based FPGAs, the ECP2M provides the only low cost implementation alternative for PCI Express, Ethernet, Serial RapidIO and CPRI/OBSAI based applications.

LatticeEP2M SERDES Features & Benefits

• Up to 16 Channels of Packet Based SERDES
  • 270Mbps to 3.125 Gbps per channel 
  • High RX jitter Tolerance (0.8UI at 2.5G) 
  • Low TX jitter (0.24 UI at 2.5G) 
  • Low Power (100 mW per channel typical) 
  • SERDES Only mode allows direct 8 /10/16/20-bit interface to FPGA logic
• Cost Effective Physical Coding Sublayer (PCS)
  • Up to 16 Channels of full-duplex data supported per device 
  • Support for Popular Packet Based Standards 
  • Support for generic 8b/10b encoding/decoding 
  • Built-in link synchronization state machine, rate matcher and Gigabit Ethernet State Machine
• PCI Express Solutions
  • Integrated hardware with SERDES and low cost FPGA fabric 
  • Electromechanically compliant Evaluation Board
  • Lattice supplied software drivers and API
  • Lowest cost PCI Express endpoint solution in the industry
• Gigabit Ethernet Solutions
  • Single channel provides 1G Ethernet link to GMII compliant FPGA logic interface 
  • Access Clause 22 PHY registers in Auto-negotiation mode 
  • Comma character word alignment 
  • Clock Tolerance Compensation circuit (Rate Matcher) 
  • Lattice supplied Triple Speed MAC soft IP
  • Lowest cost Gigabit Ethernet solution in the industry