Pre-Engineered Source Synchronous Interfaces

Increased Use Of Source Synchronous Interfaces

Designers are increasingly using source synchronous interfaces. This increased use is driven by many factors such as the need to use low cost DDR1 or 2 DRAM memory, the desire to interface with high-speed ADCs and DACs or the need to interface with a number of communication standards such as SPI4.2.

Source Synchronous Interface Challenges

While the use of source synchronous interfaces is often necessary to meet performance and cost targets they have represented a significant challenge to users of FPGAs, especially low cost FPGAs. Although the specifics vary with each interface typical challenges include:

• Converting DDR (Double Data Rate) Data Streams into SDR (Single Data Rate)
• Matching the I/O and FPGA Fabric Data Rates
• Aligning the Data Clock (Often Referred to as a Strobe or DQS Signal) with the Data
• Transferring Data from the Interface Clock Domain to the FPGA Clock Domain

LatticeECP2/M Devices Provide Pre-Engineered Source Synchronous Interfaces

The I/O cells in the LatticeECP2/M devices contain a number of pre-engineered elements to allow the easy implementation of source synchronous interfaces such as those found on DDR1/2 memories, SPI4.2 systems and high speed ADC/DACs.

• Precision DQS/Strobe Delay Control
• Dedicated DDR Registers (For Mux and Demuxing)
• Automatic DQS to System Clock Transfer
• 2:1 Gearbox Logic to Match I/O Speed with FPGA Fabric
• Low Skew Edge Clocks

The elements highlighted above can easily be combined in the ispLEVER tool to implement a variety of interfaces including 533Mbps DDR1/2 memory interfaces, 750Mbps SPI4.2 interfaces and 840Mbps generic source synchronous interfaces.