Optimized FPGA Architecture for Low Cost Applications

The LatticeECP2/M family has a silicon efficient FPGA fabric in which I/O capability, distributed memory, embedded memory, logic and routing have been optimized to provide the best features at value-conscious prices. The following diagrams provides an overview of the LatticeECP2/M architecture. Additional details on all of the blocks can be found in the device datasheet.

Lattice ECP2M Block Diagram

Lattice ECP2 Block Diagram

Features Not Shown on Diagrams

• Eight Global clock nets
• Eight Regional clocks
• Two Edge Clocks per side