Lowest Power SERDES-based FPGA

Lower power operation helps you meet your thermal and reliability requirements and reduce your overall system cost and design complexity.

Compared to LatticeECP, LatticeECP2M devices offer on average, ~ 50% lower static power. As shown in figure 1, at 25°C junction temperature, the largest LatticeECP2M device, the 95K LUT ECP2M-100, consumes less than 0.35W of power.

The power advantage is achieved by using various process and architectural enhancements as well as software power optimization techniques. These include using variable channel length transistors and multi-threshold transistors to reduce the leakage current where performance is not critical, and implementing improved routing defaults & algorithms in the software to minimize power.

Figure 1: Typical Power Consumption for LatticeECP2M Devices

Figure 2 shows typical static power consumption for LatticeECP2M and competing FPGAs. LatticeECP2M devices consume up to 65% lower static power than competing FPGA devices.

Figure 2: Static Power Consumption of LatticeECP2M vs. Competing FPGAs

Power Estimation and Analysis Tools

• ispLEVER Power Calculator
• Power Estimation and Management for LatticeECP2M Devices Technical Note