ispClock

IF (time = money), THEN (use ispClock)

Time waits for no silicon – Why waste time with zero-delay buffers, fan-out buffers, termination resistors, delay lines and serpentine clock trace layouts when ispClock devices can replace them all?

Even a stopped clock tells the right time twice a day – ispClock devices can be programmed in-system to generate multiple clock frequencies and drive clock nets with different signalling requirements.

Time stream compensation – Compensate for output differences in clock trace lengths, precisely match trace impedances and drive clock nets with different signalling requirements – all while meeting stringent skew and jitter standards.

Features

  • Available in multiple formats: ispClock5600A for clock generation, ispClock5400D for differential clock distribution and ispClock5300S for single-ended clock distribution
  • Reduce board space – a single ispClock replaces multiple types of clock devices
  • Maximum cycle-cycle jitter 70 ps (peak-peak)
  • Maximum phase jitter 50 ps
  • Support multiple interface types including: LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Diff. SSTL, Diff. HSTL

Family Table

ispClock Product Family Selector Guide

Feature ispClock5600A Family ispClock5400D Family ispClock5300S Family
Outputs 20 or 10 10 or 6 20, 16, 12, 8, or 4
Input Operating Frequency Range 8 to 400MHz 50 TO 400MHz 8 to 267MHz
Output Operating Frequency Range 4 to 400MHz 50 TO 400MHz 5 to 267MHz
VCO Operation 320 to 800MHz 400 TO 800MHz 160 to 400MHz
Spread Spectrum Compatibility Yes Yes Yes
Single-Ended Fan-out Buffer Interfaces LVTTL, LVCMOS, HSTL, eHSTL, SSTL None LVTTL, LVCMOS, HSTL, eHSTL, SSTL
Single-Ended Clock Reference and Feedback Interfaces LVTTL, LVCMOS, SSTL, HSTL LVCMOS LVTTL, LVCMOS, HSTL, eHSTL, SSTL
Differential Fan-out Buffer Interfaces SSTL, HSTL, LVDS, LVPECL LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS None
Differential Clock Reference and Feedback Interfaces HSTL, SSTL, LVDS, LVPECL LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS LVDS, LVPECL, HSTL, SSTL
Type of PLL Feedback Internal/External Internal/External External
M, N Dividers Count from 1 to 40 None None
Number of V Dividers 5 4 3
V Divider Count Range 2 to 80 (in steps of 2) 2 to 16 (in powers of 2) 1 to 32 (in powers of 2)
Maximum Cycle-Cycle Jitter 70ps (peak-peak) 29ps (peak-peak) 70ps (peak-peak)
Maximum Period Jitter (RMS) 12ps 2.5ps 12ps
Maximum Phase Jitter (RMS) 50ps 6ps Typ. 50ps
Maximum Static Phase Offset -100ps to 200ps -5ps to 95ps -40ps to 100ps
Frequencies Generated 5 4 3
Programmable Phase Skew 156ps to 12ns 156ps to 12ns 156ps to 5ns
Programmable Time Skew None 0ps to 288ps None
Fan-out Buffer Mode No Yes Yes
Programmable Termination 40 to 70Ω & 20Ω Setting None 40 to 70Ω & 20Ω Setting

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Application Notes

Learn how to get the most from our line-up of FPGAs / development boards

Software

Complete Design Flows, High Ease of Use

Development Kits & Boards

Our development boards & kits help streamline your design process

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Documentation

Quick Reference Technical Resources Information Resources Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
ispClock 5600 Family Data Sheet Revision History
2/1/2005 PDF 8 KB
ispClock 5600A Family Data Sheet
DS1019 01.4 6/3/2008 PDF 969.3 KB
ispClock5300S Data Sheet
DS1010 01.4 10/1/2007 PDF 1.2 MB
ispClock5400D Family Data Sheet
DS1025 01.3 12/14/2011 PDF 1.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Driving SERDES Reference Clocks with the ispClock5400D Differential Clock Buffer
AN6081 01.0 10/6/2009 PDF 741.8 KB
Interfacing ispClock5600A with Reference Clock Oscillators
AN6079 01.0 8/6/2008 PDF 513.5 KB
ispClock5620 Evaluation Board ispPAC-CLK5620-EV1
AN6064 10/31/2004 PDF 1019.1 KB
ispClock5620A Evaluation Board: ispPAC-CLK5620A-EV1
Describes the features and operation of the ispPAC-CLK5620A-EV1 evaluation board.
AN6072 3/1/2007 PDF 929.7 KB
Using a Low-Cost CMOS Oscillator as a Reference Clock for SERDES Applications
AN6080 01.1 2/13/2012 PDF 202.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Generating a Single-Ended Clock Source from ispClock5400D Differential Clock Buffers - Source Code
RD1069 1.0 1/22/2010 ZIP 129.9 KB
Generating a Single-Ended Clock Source from ispClock5400D Differential Clock Buffers Reference Design - Documentation
RD1069 1.0 1/22/2010 PDF 171.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
ACN03D-11 Withdrawal of ACN03C-11
ANC03D-11 1 4/1/2011 PDF 796.6 KB
PCN 02A-15 Affected_OPN_Listing
3.0 8/12/2015 XLSX 310.4 KB
PCN 02A-15 SnPb and Select Mature Family Discontinuance
1.0 6/18/2015 PDF 316.9 KB
PCN02A-15 Frequently Asked Questions
2.0 6/18/2015 DOCX 60.8 KB
PCN06C-11 Withdrawal of PCN06B-11
PCN06C-11 1.0 8/1/2011 PDF 838.5 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice OrCAD Capture Schematic Library (OLB)
This file contains a OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
5.7 12/22/2016 ZIP 898.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
ispClock Product Brief
I0168E 12/5/2007 PDF 611.2 KB
ispClock Product Brief For Rebranding
8/16/2013 PDF 265 KB
ispClock5300S Product Brief
I0193 10/31/2012 PDF 1.1 MB
ispClock5400D Product Brief
I0200 11/1/2012 PDF 544.5 KB
Power Manager II and ispClock Application Examples
I0191 8/1/2007 PDF 456.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
32 QFNS Pb-Free Device Material Content
Includes all 3 versions
D 4/19/2016 PDF 51.1 KB
Lattice ispCLOCK Product Family Qualification Summary
A 7/1/2009 PDF 383.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Dynamic Power Management in an Embedded System
3/31/2005 PDF 619.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
[BSDL ISC] ispCLOCK5304S 48 Pin TQFP
1.00 3/1/2007 BSM 15.4 KB
[BSDL ISC] ispCLOCK5308S 48 Pin TQFP
1.00 3/1/2007 BSM 15.4 KB
[BSDL ISC] ispCLOCK5312S 48 Pin TQFP
1.00 3/1/2007 BSM 15.7 KB
[BSDL ISC] ispCLOCK5316S 64 Pin TQFP
1.00 3/1/2007 BSM 17.2 KB
[BSDL ISC] ispCLOCK5320S 64 Pin TQFP
1.00 3/1/2007 BSM 17.4 KB
[BSDL ISC] ispCLOCK5510v 48 Pin TQFP
1.00 3/31/2005 BSM 17.8 KB
[BSDL ISC] ispCLOCK5520v 100 Pin TQFP
1.00 3/31/2005 BSM 19.1 KB
[BSDL ISC] ispCLOCK5610Av 48 Pin TQFP
1.01 4/21/2006 BSM 18.4 KB
[BSDL ISC] ispCLOCK5610v 48 Pin TQFP
1.01 6/1/2005 BSM 18.1 KB
[BSDL ISC] ispCLOCK5620Av 100 Pin TQFP
1.01 4/21/2006 BSM 20.1 KB
[BSDL ISC] ispCLOCK5620v 100 Pin TQFP
1.02 6/1/2005 BSM 19.8 KB
[BSDL] ispCLOCK5304S 48 Pin TQFP
1.00 3/1/2007 BSM 10 KB
[BSDL] ispCLOCK5308S 48 Pin TQFP
1.00 3/1/2007 BSM 10.3 KB
[BSDL] ispCLOCK5312S 48 Pin TQFP
1.00 3/1/2007 BSM 10.6 KB
[BSDL] ispCLOCK5316S 64 Pin TQFP
1.00 3/1/2007 BSM 12.3 KB
[BSDL] ispCLOCK5320S 64 Pin TQFP
1.00 3/1/2007 BSM 12.2 KB
[BSDL] ispCLOCK5406D 48 Pin TQFP
1.00 1/1/2009 BSM 12.3 KB
[BSDL] ispCLOCK5410D 64 Pin TQFP
1.00 1/1/2009 BSM 13 KB
[BSDL] ispCLOCK5510v 48 Pin TQFP
1.02 3/31/2005 BSM 13.4 KB
[BSDL] ispCLOCK5520v 100 Pin TQFP
1.02 3/31/2005 BSM 14.7 KB
[BSDL] ispCLOCK5610Av 48 Pin TQFP
1.01 4/21/2006 BSM 13.3 KB
[BSDL] ispCLOCK5610v 48 Pin TQFP
1.01 6/1/2005 BSM 13.2 KB
[BSDL] ispCLOCK5620Av 100 Pin TQFP
1.01 4/21/2006 BSM 15 KB
[BSDL] ispCLOCK5620v 100 Pin TQFP
1.01 6/1/2005 BSM 15.2 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
[IBIS] ispPAC-CLK5304S/5308S/5312S/5316S/5320S
0.2 2/1/2007 IBS 11.6 MB
[IBIS] ispPAC-CLK5610AV/5620AV
0.3 7/1/2006 IBIS 11.8 MB


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