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Related To
Topic ID Family Article Type Category Related To
TESTINGHow to use Reveal on CrossLink/LIFMD device for debugging the design? 5841 CrossLink faq Customer Board Design Board Debug
Why ispMACH datasheet didn't provide rise and fall time? 5835 ispMACH 4000 faq
Why TRACE did not detect violation in LSR pin, but during simulation, it was detected? 5819 MACHXO3 faq
Why is there no Hi-z on soft D-PHY ports during boot up? 5800 CrossLink faq
Why does Run Place in iceCube errors "Feasibility check for IO Placement failed"? 5792 iCE40 Ultra faq Debugging
How can I set implementation properties in the TCL Console? 5790 LatticeECP5 faq
No.1- Case of using "mipi_dphy ver1.1" on Cross Link1. What clock do we need to input... 5784 CrossLink faq Lattice IP/Reference Design IP/Reference Design Inquiries
How should RX port be biased with AC coupling? 5759 ASSP-Wired (Silicon Image) faq
When instantiating SB_IO primitive with PIN_TYPE = 110100, why does Place and Route... 5747 iCE40 Ultra faq Architecture IO
Why are there an Error ID 67 and 27 shown in the report when compiling a design? 5740 Power Manager II faq Device Programming PAC-Designer
How safe is the device configuration at power-up? 5739 iCE40 Ultra Lite faq
Why is Mixel IP datasheet not available? What are CO, CN, CM? 5680 CrossLink faq Lattice IP/Reference Design IP/Reference Design Inquiries
Why are there Insufficient Primary Clock Resources for 2:1 MIPI stitching with I2C? 5676 CrossLink faq Architecture PLL/DLL/Clock Routing
Can we program USERCODE without erasing NVCM0? 5662 MACHXO3 faq
Q1: Is it possible to modify the I2C traffic? Or you need to break the I2C bus and... 5556 Other FPGA faq Device Programming Lattice Evaluation Boards
Do you still have  BSDL data for SiI3132? 5436 Other Mixed Signal faq
Can a task for CPU embedded programming of FPGA be interrupted on the CPU during... 2493 All FPGA faq Device Programming ispVM Embedded
Can the Master SPI Mode(MSPI) be used to access the on-chip Flash memory of MachXO2... 1905 MachXO2 faq Device Programming Configuration/Programming
Each of the I/O pins on the MachXO2 devices has a clamp. Is this clamp, PCI compliant? 1879 MachXO2 faq Architecture IO
What time does VCCINT, which is regulated from the VCC become stable? 1768 MachXO2 faq Architecture Configuration/Programming
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