I2C Master - WISHBONE Compatible

Reference Design LogoThis reference design is based on the OpenCores I2C master core and provides a bridge between the I2C and WISHBONE bus. A typical application of this design includes the interface between a WISHBONE compliant on-board microcontroller and multiple I2C peripheral components. The I2C master core generates the clock and is responsible for the initiation and termination of each data transfer.

I2C (Inter-Integrated Circuit) Master - WISHBONE Compatible

 

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Performance and Size

Device Family Tested Devices* Performance I/O Pins Design Size Revision
MachXO3L™ 6 LCMXO3L-4300C-
6BG256C
>50MHz 29 201 LUTs(Verilog-LSE Source) 1.5
243 LUTs (Verilog-Syn Source) 1.5
218 LUTs (VHDL-LSE Source) 1.5
243 LUTs (VHDL-Syn Source) 1.5
MachXO2™ 1 LCMXO2-1200HC-
4TG100C
>50MHz 29 201 LUTs (Verilog Source)
218 LUTs (VHDL Source)
1.5
MachXO™ 2 LCMXO256C-
3T100C
>50MHz 29 198 LUTs (Verilog Source)
217 LUTs (VHDL Source)
1.5
ECP5™ 5 LFE5U-45F-
6MG285C
>50MHz 29 203 LUTs (Verilog Source)
209 LUTs (VHDL Source)
1.5
LatticeECP3™ 3 LFE3-17EA-
6FTN256C
>50MHz 29 261 LUTs (Verilog Source)
252 LUTs (VHDL Source)
1.5
LatticeXP2™ 4 LFXP2-5E-
5M132C
>50MHz 29 252 LUTs (Verilog Source)
248 LUTs (VHDL Source)
1.5

1. Performance and utilization characteristics are generated using LCMXO2-1200HC-4TG100C with Lattice Diamond® 3.1 design software with LSE (Lattice Synthesis Engine).
2. Performance and utilization characteristics are generated using LCMXO256C-3T100C with Lattice Diamond 3.1 design software with LSE.
3. Performance and utilization characteristics are generated using LFE3-17EA-6FTN256C with Lattice Diamond 3.1 design software.
4. Performance and utilization characteristics are generated using LFXP2-5E-5M132C with Lattice Diamond 3.1 design software.
5. Performance and utilization characteristics are generated using LFE5U-45F-6MG285C with Lattice Diamond 3.1 design software with LSE.
6. Performance and utilization characteristics are generated using LCMXO3L-4300C-6BG256C with Lattice Diamond 3.1 design software with LSE and Synplify Pro®.

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
I2C Master with WISHBONE Bus Interface - Documentation
RD1046 1.6 1/15/2015 PDF 1.4 MB
I2C Master with WISHBONE Bus Interface - Source Code
RD1046 1.8 2/1/2016 ZIP 1.4 MB


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