MIPI DSI Transmit Bridge

A Complete HDL Reference Design

The Lattice Semiconductor DSI (Display Serial Interface) transmit reference design is a complete HDL (Hardware Description Language) design for enabling either a MachXO2, MachXO3, or ECP3 FPGA to drive a DSI receiving device. In this design, the DSI transmit accepts RGB (Red, Green & Blue) pixel bus data from a processor or other display control output device. The output of the design interfaces to a D-PHY interface IP core, allowing the FPGA to directly drive a DSI receiving device, such as a display.

The parallel RGB to DSI transmit design illustrates how Lattice Ultra Low Density FPGAs can be used to connect various processors to DSI displays. The DSI transmit design enables embedded designers to utilize low cost screens with embedded processors.

Flexible MIPI (Mobile Industry Processor Interface) DSI Transmit Bridge - Allows an embedded processor that does not have mobile I/O to interface to a low cost DSI screen.

MIPI Application Diagram

Features

  • Supports up to 4 data lanes at up to ~ 900Mbps per lane
  • HS (High Speed) Mode transmit
  • LP (Low Power) Mode transmit and receive
  • Typical power for 2 data lane bridge running at 700Mbps is 20mW
  • Typical power for 4 data lane bridge running at 700Mbps is 32mW
  • DCS (Display Command Set) controller to program the display
  • Supports DSI formats RGB, YCbCr and User Defined
  • Input parallel RGB bus supporting up to 36 bits with clock, Hsync & Vsync

Block Diagram

Documentation

Quick Reference Technical Resources Information Resources
  TITLE NUMBER VERSION DATE FORMAT SIZE
MIPI D-PHY Bandwidth Matrix Table User Guide UG110 1.0 6/30/2015 PDF 1.3 MB
MIPI DPHY DSI/CSI-2 Example Schematic 1.0 10/29/2013 PDF 72.6 KB
  TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeECP3 RGB888 2L RD1184 2.0 8/18/2015 ZIP 1.3 MB
LatticeECP3 RGB888 4L RD1184 2.0 8/18/2015 ZIP 1.4 MB
LatticeECP5 RGB888 4L RD1184 2.0 8/18/2015 ZIP 1.4 MB
LatticeXP2 RGB888 4L RD1184 2.0 8/18/2015 ZIP 1.4 MB
MachXO2 RGB101010 1L RD1184 2.0 8/18/2015 ZIP 1.3 MB
MachXO2 RGB565 1L RD1184 2.0 8/18/2015 ZIP 1.2 MB
MachXO2 RGB565 4L RD1184 2.0 8/18/2015 ZIP 1 MB
MachXO2 RGB666 1L RD1184 2.0 8/18/2015 ZIP 2.4 MB
MachXO2 RGB888 1L RD1184 2.0 8/18/2015 ZIP 1.2 MB
MachXO2 RGB888 2L RD1184 2.0 8/18/2015 ZIP 1.3 MB
MachXO2 RGB888 4L RD1184 2.0 8/18/2015 ZIP 1.3 MB
MachXO2 YCbCr420 12b 1L RD1184 2.0 8/18/2015 ZIP 911.7 KB
MachXO2 YCbCr422 16b 1L RD1184 2.0 8/18/2015 ZIP 1.2 MB
MachXO2 YCbCr422 16b 2L RD1184 2.0 8/18/2015 ZIP 1.2 MB
MachXO2 YCbCr422 24b 4L RD1184 2.0 8/18/2015 ZIP 2.5 MB
MachXO3 RGB101010 1L RD1184 2.0 8/18/2015 ZIP 1.3 MB
MachXO3 RGB666 1L RD1184 2.0 8/18/2015 ZIP 1.2 MB
MachXO3 RGB888 1L RD1184 2.0 8/18/2015 ZIP 1.2 MB
MachXO3 RGB888 2L RD1184 2.0 8/18/2015 ZIP 1.3 MB
MachXO3 RGB888 4L RD1184 2.0 8/18/2015 ZIP 1.3 MB
MachXO3 YCbCr422 24b 4L RD1184 2.0 8/18/2015 ZIP 1.4 MB
MIPI D-PHY Interface IP - Documentation RD1182 1.5 1/31/2015 PDF 3 MB
MIPI D-PHY Interface IP - Source Code RD1182 1.5 1/31/2015 ZIP 4.2 MB
Parallel to MIPI DSI TX Bridge - Documentation RD1184 1.5 1/1/2015 PDF 1.6 MB
Parallel to MIPI DSI TX Bridge - Source Code RD1184 1.5 1/1/2015 ZIP 2.6 MB
  TITLE NUMBER VERSION DATE FORMAT SIZE
MIPI Display Serial Interface Solution Product Flyer Rev. 2 10/22/2013 PDF 1.8 MB
  TITLE NUMBER VERSION DATE FORMAT SIZE
Multi-time Programmable ULD FPGAs 1.0 12/1/2013 PDF 163.5 KB

If you need a MIPI configuration which doesn't appear as a reference design on this page, contact your local Lattice Sales Office.