The Lattice Semiconductor DSI (Display Serial Interface) transmit reference design is a complete HDL (Hardware Description Language) design for enabling either a MachXO2, MachXO3, or ECP3 FPGA to drive a DSI receiving device. In this design, the DSI transmit accepts RGB (Red, Green & Blue) pixel bus data from a processor or other display control output device. The output of the design interfaces to a D-PHY interface IP core, allowing the FPGA to directly drive a DSI receiving device, such as a display.
The parallel RGB to DSI transmit design illustrates how Lattice Ultra Low Density FPGAs can be used to connect various processors to DSI displays. The DSI transmit design enables embedded designers to utilize low cost screens with embedded processors.
Flexible MIPI (Mobile Industry Processor Interface) DSI Transmit Bridge - Allows an embedded processor that does not have mobile I/O to interface to a low cost DSI screen.
- Supports up to 4 data lanes at up to ~ 900Mbps per lane
- HS (High Speed) Mode recevie
- LP (Low Power) Mode transmit and receive
- Typical power for 2 data lane bridge running at 700Mbps is 20mW
- Typical power for 4 data lane bridge running at 700Mbps is 32mW
- Provides a DCS (Display Command Set) encoder for display controls
- Supports DSI formats RGB, YCbCr and User Defined
- Output parallel RGB bus supporting up to 36 bits with clock, Hsync & Vsync