MIPI CSI-2 Transmit Bridge

A Complete HDL Reference Design

MIPI (Mobile Industry Processor Interface) based application processors (APs) can be used for a multitude of designs outside of the consumer mobile market place because they offer tremendous integration, low power and low cost. However, if an AP needs to interface to an image sensor that is not designed for mobile applications, then conversion bridge logic is required. Image sensors targeting the embedded or digital still camera markets, for example, often have subLVDS or other proprietary interfaces that are not CSI-2 (Camera Serial Interface). The parallel to CSI-2 transmit reference design enables designers to easily implement the bridging function in a Lattice Semiconductor FPGA.

The parallel to CSI-2 transmit design underscores how Lattice Ultra Low Density FPGAs can connect various image sensors to APs or image sensor processors (ISPs).

Flexible MIPI CSI-2 Transmit Bridge - The CSI-2 transmit design enables embedded designers to utilize low cost APs or even ISPs with embedded image sensors.

MIPI CMOS Diagram

Features

  • Interfaces to MIPI CSI-2 Receiving Devices
  • Supports up to 4 data lanes at up to ~ 900Mbps per lane
  • Typical power for 2 data lane bridge running at 700Mbps is 20mW
  • Typical power for 4 data lane bridge running at 700Mbps is 32mW
  • Unidirectional HS (High Speed) Mode Support
  • Bidirectional LP (Low Power) Mode Support
  • Various pixel bus bit width on the input accepted
  • Support for CSI-2 compatible video formats (RAW, YUV or RGB supported)

Block Diagram

Documentation



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