MIPI CSI-2 Transmit Bridge

A Complete HDL Reference Design

MIPI (Mobile Industry Processor Interface) based application processors (APs) can be used for a multitude of designs outside of the consumer mobile market place because they offer tremendous integration, low power and low cost. However, if an AP needs to interface to an image sensor that is not designed for mobile applications, then conversion bridge logic is required. Image sensors targeting the embedded or digital still camera markets, for example, often have subLVDS or other proprietary interfaces that are not CSI-2 (Camera Serial Interface). The parallel to CSI-2 transmit reference design enables designers to easily implement the bridging function in a Lattice Semiconductor FPGA.

The parallel to CSI-2 transmit design underscores how Lattice Ultra Low Density FPGAs can connect various image sensors to APs or image sensor processors (ISPs).

Flexible MIPI CSI-2 Transmit Bridge - The CSI-2 transmit design enables embedded designers to utilize low cost APs or even ISPs with embedded image sensors.

MIPI CMOS Diagram

Custom Configuration - Click the start here button below and complete the CSI-2 Tx configuration form. We will send you a HDL (Hardware Description Language) netlist for your specific CSI-2 Tx requirements.

Click here to begin

Alternatively you can download the default design which bridges from a parallel pixel bus to 2 lane RAW 10 bit mode.

  • Interfaces to MIPI CSI-2 Receiving Devices
  • Up to 4 data lanes of CSI-2 at up to ~ 800Mbps 
  • Typical power for 2 data lane bridge running at 700Mbps is 20mW
  • Typical power for 4 data lane bridge running at 700Mbps is 32mW
  • Unidirectional HS (High Speed) Mode Support
  • Bidirectional LP (Low Power) Mode Support
  • Various pixel bus bit width on the input accepted
  • Support for CSI-2 compatible video formats (RAW, YUV or RGB supported)

MIPI CSI-2 Transmit Bridge Product Brochure

  TITLE NUMBER VERSION DATE FORMAT SIZE
MIPI Display Serial Interface Solution Product Flyer 12.2 10/22/2013 PDF 1.1 MB

MIPI CSI-2 Transmit Bridge User Manual

  TITLE NUMBER VERSION DATE FORMAT SIZE
MIPI DPHY DSI/CSI-2 Example Schematic 1.0 10/29/2013 PDF 72.6 KB

MIPI CSI-2 Transmit Bridge White Paper

  TITLE NUMBER VERSION DATE FORMAT SIZE
Multi-time Programmable ULD FPGAs 1.0 12/1/2013 PDF 163.5 KB

MIPI CSI-2 Transmit Bridge Reference Design

  TITLE NUMBER VERSION DATE FORMAT SIZE
D-PHY Reference Design RD1182 7/31/2013 ZIP 2.9 MB
MIPI D-PHY Interface IP - Documentation RD1182 1.3 1/2/2014 PDF 2.9 MB
Parallel to MIPI CSI-2 TX Bridge - Documentation RD1183 1.4 4/2/2014 PDF 1.2 MB
Parallel to MIPI CSI-2 TX Bridge - Source Code RD1183 1.4 4/1/2014 ZIP 909.6 KB