MachXO3 Chip Shot

MachXO3 FPGA Family

Most Advanced, Lowest Cost per I/O Programmable Bridging and I/O Expansion Solution

Breakthrough I/O Density at the Lowest Cost per I/O – Programmable bridging and I/O expansion has never been more affordable with high I/O count priced very low.

Maximum I/O, Minimum Size – Smallest WLCSP and BGA packages with 0.4 mm, 0.5 mm and 0.8 mm ball spacing options.

Instant Programmable Bridging and I/O Expansion – Maximum flexibility with instant-on access and multi-time programmability.

Testing 4

MachXO3 devices are Lattice’s newest instant-on, non-volatile, small footprint FPGAs. The MachXO3L FPGA family features the latest in advanced small packaging technology, low power, and aggressive cost combined with fast performance. The MachXO3L FPGA family spans from 640 to 6900 LUTs. It is available in lower power E (1.2 V core) version or C (3.3/2.5 V core) versions. Some of the key MachXO3L FPGA family features are:

Amazingly small packages

  • 0.4 mm pitch wafer level chip scale packages from 2.5 x 2.5 mm to 3.8 x 3.8 mm
  • 0.5 mm pitch BGAs that deliver maximum I/O, small size and low cost
  • 0.8 mm pitch BGAs that provide highest I/O count at lowest cost/IO

Need to bridge MIPI DSI or CSI-2?

  • Complete reference designs available
  • Low power and small sizes allow use in consumer products
  • Allows bridging to / from legacy interfaces

Maximum Control. Minimum Boot-up.

  • Instant-on 1 ms boot-up
  • Low voltage core 1.2 V or choose a single 3.3/2.5 V power supply
  • Hysteresis on inputs provides noise immunity with slow signals

Built in hard functions

  • Timer counter
  • Two I2C interfaces
  • SPI interface
  • Programmable Oscillator

MachXO3L Device Selection Guide

PARAMETERS XO3L-640 XO3L-1300 XO3L-2100 XO3L-4300 XO3L-6900
Density LUTs 640 1300 2100 4300 6900
EBR RAM (kbits) 64 64 74 92 240
PLL 1 1 1 2 2
Multi Time Programmable NVCM Yes Yes Yes Yes Yes
1 x SPI controller, 2 x I2C controller Yes Yes Yes Yes Yes
1 x Oscillator, 1 x Timer/Counter Yes Yes Yes Yes Yes
MIPI D-PHY Support Yes Yes Yes Yes Yes
Packages
36-ball WLCSP (0.4, 2.5 x 2.5) 28
49-ball WLCSP (0.4, 3.2 x 3.2) 38
81-ball WLCSP (0.4, 3.8 x 3.8) 63
121-ball csfBGA (0.5, 6 x 6) 100 100 100 100
256-ball csfBGA (0.5, 9 x 9) 206 206 206 206
324-ball csfBGA (0.5, 10 x 10) 267 267 281
256-ball caBGA (0.8, 14 x 14) 206 206 206 206
324-ball caBGA (0.8, 15 x 15) 279 279 279
400-ball caBGA (0.8, 17 x 17) 335 335

CSI-2 Image Sensor Interfacing

  • Supports CSI-2 High Speed Differential Signaling
    • Both Rx and Tx interfaces
  • From 1-4 lanes of CSI-2 at up to 800 Mbps
  • Can be implemented in a 49 wlcsp (3.2 x 3.2 mm)
  • RAW, YUV or RGB supported

DSI LCD Display Interfacing

  • Supports DSI transmit signaling
    • HS (High Speed) Mode transmit
    • LP (Low Power) Mode transmit and receive
  • Can be implemented in a 49 wlcsp (3.2 x 3.2 mm)
  • Supports DSI formats RGB, YCbCr and User Defined
  • Input bus can also be DSI to enable LCD screen replacement

Microprocessor Interface Expansion

  • Save cost by adding GPIO to low-cost microcontrollers
  • Add additional SPI and I2C interfaces to system control processors
  • Perform voltage level translation with ease
  • Simplify system management with PLD implementation of system status registers

Lattice Diamond Design Software

Leading-edge design software for Lattice FPGA families. Upgrade your design process with an easy-to-use interface, superior design exploration, optimized design flow, Tcl scripting and more. Click here to view more information.

MachXO3 FPGA Family Application Note

  TITLE NUMBER VERSION DATE FORMAT SIZE
Implementing High-Speed Interfaces with MachXO3L Devices TN1281 1.0 12/18/2013 PDF 4.5 MB
MachXO3L Hardware Checklist TN1291 1.0 4/23/2014 PDF 283 KB
MachXO3L Programming and Configuration Usage Guide TN1279 1.2 7/21/2014 PDF 3.9 MB
MachXO3L SED Usage Guide TN1292 1.0 4/23/2014 PDF 710.4 KB
MachXO3L sysCLOCK PLL Design and Usage Guide TN1282 1.0 12/18/2013 PDF 4.4 MB
MachXO3L sysIO Usage Guide TN1280 1.2 8/12/2014 PDF 2 MB
Memory Usage Guide for MachXO3L Devices TN1290 1.0 4/23/2014 PDF 5.5 MB
Power Estimation and Management for Mach XO3L Devices TN1289 1.1 7/3/2014 PDF 1.2 MB
Thermal Management 2.3 5/14/2014 PDF 843.7 KB
Using Hardened Control Functions in MachXO3L Devices TN1293 1.0 4/23/2014 PDF 2.9 MB
Using Hardened Control Functions in MachXO3L Devices Reference Guide TN1294 1.1 7/21/2014 PDF 5.7 MB
Using TraceID TN1207 1.6 6/24/2014 PDF 732.5 KB
Using TransFR Technology TN1087 3.5 3/4/2014 PDF 2.4 MB
Wafer-Level Chip-Scale Package Guide TN1242 1.0 7/13/2011 PDF 127.2 KB

MachXO3 FPGA Family Data Sheet

  TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO3 256-Pin caBGA Package Migration File 2.0 5/27/2014 CSV 40.6 KB
MachXO3 400-caBGA Package Migration File 1.0 6/23/2014 CSV 23.3 KB
MachXO3L 1300 Pinout 256 Ball 1.0 6/23/2014 CSV 14 KB
MachXO3L 2100 Pinout 324 Ball 1.0 6/23/2014 CSV 17.8 KB
MachXO3L 4300 Pinout 400 Ball 1.0 6/23/2014 CSV 20.7 KB
MachXO3L Family Data Sheet DS1047 1.1 7/17/2014 PDF 5.4 MB
MachXO3L121 csfBGA Pin Migration 1.0 6/23/2014 CSV 34.7 KB
MachXO3L-1300 Pinout 1.0 6/23/2014 CSV 13 KB
MachXO3L-2100 Pinout 1.1 6/23/2014 CSV 15.9 KB
MachXO3L256 csfBGA Pin Migration 1.0 6/23/2014 CSV 40.7 KB
MachXO3L-324 caBGA Pin Migration 1.0 6/23/2014 CSV 33.9 KB
MachXO3L324 csfBGA Pin Migration 1.0 6/23/2014 CSV 33.6 KB
MachXO3L-640 Pinout 1.0 6/23/2014 CSV 12.3 KB
MachXO3L-6900 Pinout 1.1 6/23/2014 CSV 28 KB
MaxhXO3L-4300 Pinout 1.1 6/23/2014 CSV 23.2 KB
Package Diagrams 4.5 8/14/2014 PDF 13.6 MB

MachXO3 FPGA Family Product Brochure

  TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO3L Product Brief I0238 2/1/2014 PDF 1.1 MB
MIPI Display Serial Interface Solution Product Flyer 12.2 10/22/2013 PDF 1.1 MB

MachXO3 FPGA Family Quality Assurance

  TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO3L Product Family Qualification Summary B 8/4/2014 PDF 673.6 KB

MachXO3 FPGA Family Schematic Symbols

  TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice OrCAD Capture Schematic Library (OLB) 4.0 7/16/2014 ZIP 946.6 KB

MachXO3 FPGA Family White Paper

  TITLE NUMBER VERSION DATE FORMAT SIZE
Leveraging MIPI D-PHY-based Peripherals in Embedded Designs 1.0 5/1/2014 PDF 567.3 KB
Multi-time Programmable ULD FPGAs 1.0 12/1/2013 PDF 163.5 KB

MachXO3 FPGA Family BSDL Model

  TITLE NUMBER VERSION DATE FORMAT SIZE
[BSDL] LCMXO3L1300E CSFBGA121 1.5 6/17/2014 BSM 25.4 KB
[BSDL] LCMXO3L1300E WLCSP36 1.5 6/17/2014 BSM 18.9 KB
[BSDL] LCMXO3L2100C CABGA256 1.5 6/17/2014 BSM 42.7 KB
[BSDL] LCMXO3L2100C CABGA324 1.5 6/17/2014 BSM 53.3 KB
[BSDL] LCMXO3L2100E CSFBGA121 1.5 6/23/2014 BSM 32.9 KB
[BSDL] LCMXO3L2100E CSFBGA256 1.5 6/23/2014 BSM 42.6 KB
[BSDL] LCMXO3L2100E CSFBGA324 1.5 6/23/2014 BSM 52.7 KB
[BSDL] LCMXO3L2100E WLCSP49 1.5 6/23/2014 BSM 27.1 KB
[BSDL] LCMXO3L4300 ECSFBGA256 1.5 6/23/2014 BSM 47.2 KB
[BSDL] LCMXO3L4300C CABGA256 1.5 6/23/2014 BSM 47.3 KB
[BSDL] LCMXO3L4300C CABGA324 1.5 6/23/2014 BSM 53.3 KB
[BSDL] LCMXO3L4300C CABGA400 1.5 6/23/2014 BSM 53.3 KB
[BSDL] LCMXO3L4300E CSFBGA121 1.5 6/23/2014 BSM 37.5 KB
[BSDL] LCMXO3L4300E CSFBGA324 1.5 6/23/2014 BSM 52.7 KB
[BSDL] LCMXO3L640E CSFBGA121 1.5 6/17/2014 BSM 25.4 KB
[BSDL] LCMXO3L6900C CABGA256 1.5 6/23/2014 BSM 51.2 KB
[BSDL] LCMXO3L6900C CABGA400 1.5 6/23/2014 BSM 62.4 KB
[BSDL] LCMXO3L6900E CSFBGA256 1.5 6/23/2014 BSM 51.1 KB
[BSDL] LCMXO3L6900E CSFBGA324 1.5 6/23/2014 BSM 57.2 KB
[BSDL]LCMXO3L1300E CSFBGA256 1.5 6/17/2014 BSM 25.4 KB
BSDLLCMXO3L-1300CCABGA256 1.5 6/17/2014 BSM 42.7 KB
BSDLLCMXO3L4300EWLCSP81 1.5 6/23/2014 BSM 34 KB
BSDLLCMXO3L6900CCABGA324 1.5 6/23/2014 BSM 57.2 KB

MachXO3 FPGA Family IBIS Model

  TITLE NUMBER VERSION DATE FORMAT SIZE
[IBIS] Lattice MachXO3 1.3 6/3/2014 ZIP 9.8 MB

MachXO3 FPGA Family Reference Design

  TITLE NUMBER VERSION DATE FORMAT SIZE
DSI Rx Reference Design - Documentation RD1185 1.3 4/1/2014 PDF 2.1 MB
DSI Rx Reference Design - Source Code RD1185 1.3 4/1/2014 ZIP 1.4 MB
HiSPi-to-Parallel Sensor Bridge RD1120 1.3 4/1/2014 PDF 734.9 KB
HiSPi-to-Parallel Sensor Bridge - Source Code RD1120 1.3 4/9/2014 ZIP 342.6 KB
I2C (Inter-Integrated Circuit) Master Controller - Documentation RD1005 5.8 3/6/2014 PDF 987.4 KB
I2C (Inter-Integrated Circuit) Master Controller - Source Code RD1005 5.8 3/18/2014 ZIP 1.1 MB
I2C Controller for Serial EEPROMs - Documentation RD1006 2.6 3/5/2014 PDF 767.9 KB
I2C Controller for Serial EEPROMs - Source Code RD1006 2.6 3/12/2014 ZIP 751.8 KB
I2C Master with WISHBONE Bus Interface - Documentation RD1046 1.5 3/12/2014 PDF 1.4 MB
I2C Master with WISHBONE Bus Interface - Source Code RD1046 1.4 4/12/2011 ZIP 1.4 MB
I2C Slave Peripheral using Embedded Function Block - Documentation RD1124 1.2 2/1/2014 PDF 2 MB
I2C Slave Peripheral using Embedded Function Block Reference Design RD1124 1.2 2/1/2014 ZIP 1.8 MB
I2S Controller with WISHBONE Interface Reference Design - Source Code RD1101 1.1 3/1/2014 ZIP 1.6 MB
I2S Controller with WISHBONE Interface Reference Design Documentation RD1101 1.1 3/1/2014 PDF 2.4 MB
LatticeMico8 Core - Documentation RD1026 2.0 2/1/2014 PDF 2 MB
LatticeMico8 Core Source Code RD1026 2.0 2/1/2014 ZIP 1.6 MB
LED/OLED Driver - Documentation RD1103 1.1 3/1/2014 PDF 989.6 KB
LED/OLED Driver - Source code RD1103 1.1 3/1/2014 ZIP 1.4 MB
MIPI CSI-2-to-CMOS Parallel Sensor Bridge RD1146 1.3 4/1/2014 ZIP 3.9 MB
MIPI CSI2-to-CMOS Parallel Sensor Bridge - Documentation RD1146 1.3 4/1/2014 PDF 4.2 MB
Parallel to MIPI CSI-2 TX Bridge - Documentation RD1183 1.4 4/2/2014 PDF 1.2 MB
Parallel to MIPI CSI-2 TX Bridge - Source Code RD1183 1.4 4/1/2014 ZIP 909.6 KB
Parallel to MIPI DSI TX Bridge - Documentation RD1184 1.4 4/2/2014 PDF 1.6 MB
Parallel to MIPI DSI TX Bridge - Source Code RD1184 1.4 4/1/2014 ZIP 1.2 MB
PWM Fan Controller RD1060 1.5 3/1/2014 PDF 441.1 KB
PWM Fan Controller - Source Code RD1060 1.5 3/1/2014 ZIP 326.1 KB
Read and Write Usercode - Documentation RD1041 1.3 3/1/2014 PDF 791.8 KB
Read and Write Usercode - Source Code RD1041 1.3 3/1/2014 ZIP 618.2 KB
SD Flash Controller Using SD Bus - Documentation RD1088 1.4 3/12/2014 PDF 1.4 MB
SD Flash Controller Using SD Bus - Source Code RD1088 1.4 3/12/2014 ZIP 5 MB
SDR SDRAM Controller - Documentation RD1174 1.1 3/1/2014 PDF 1.4 MB
SDR SDRAM Controller - Source Code RD1174 1.1 3/1/2014 ZIP 2.6 MB
SPI Slave Peripheral Using the Embedded Function Block RD1125 1.2 2/1/2014 PDF 1.2 MB
SPI Slave Peripheral Using the Embedded Function Block Reference Design RD1125 1.2 2/1/2014 ZIP 1.2 MB
SPI WISHBONE Controller - Documentation RD1044 1.7 3/1/2014 PDF 960 KB
SPI WISHBONE Controller - Source Code RD1044 1.7 3/1/2014 ZIP 591.1 KB
WISHBONE UART - Documentation RD1042 1.5 3/1/2014 PDF 1.4 MB
WISHBONE UART - Source Code RD1042 1.5 3/1/2014 ZIP 58.5 MB

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