MachXO3 Chip Shot

MachXO3 FPGA Family

Most Advanced, Lowest Cost per I/O Programmable Bridging and I/O Expansion Solution

Breakthrough I/O Density at the Lowest Cost per I/O – Programmable bridging and I/O expansion has never been more affordable with up to 540 I/O and priced at 1 cent per I/O.

Maximum I/O, Minimum Size – Smallest BGA packages with 0.4 mm, 0.5 mm and 0.8 mm ball spacing options.

Instant Programmable Bridging and I/O Expansion – Maximum flexibility with instant-on access and multi-time programmability.

Testing 4

MachXO3 devices are Lattice’s newest instant-on, non-volatile, small footprint FPGAs. Using advanced packaging technology to enable low cost devices, the MachXO3 portfolio consists of two families, MachXO3-L and MachXO3-H. The MachXO3-L FPGA family features the latest in small packaging, low power, and aggressive cost combined with fast performance. The MachXO3-L FPGA family spans from 640 to 6900 LUTs. It is available in lower power E (1.2 V core) version or C (3.3/2.5 V core) versions. The MachXO3-H FPGA family is a higher density family that will have more advanced features such as PCIe, Gigabit Ethernet, etc. Some of the key MachXO3-L FPGA family features are:

Amazingly small packages

  • Wafer level chip scale packages from 2.5 x 2.5 mm to 3.8 x 3.8 mm
  • 0.5 mm spaced bgas that deliver maximum I/O, small size and low cost

Need to bridge MIPI DSI or CSI-2?

  • Complete reference designs available
  • Low power and small sizes allow use in consumer products
  • Allows bridging to / from legacy interfaces

Maximum Control. Minimum Boot-up.

  • Instant-on 1 ms boot-up
  • Low voltage core 1.2 V or choose a single 3.3/2.5 V power supply
  • Hysteresis on inputs provides noise immunity with slow signals

Built in hard functions

  • Timer counter
  • Two I2C interfaces
  • SPI interface
  • Programmable Oscillator

MachXO3L Device Selection Guide

PARAMETERS XO3L-640 XO3L-1300 XO3L-2100 XO3L-4300 XO3L-6900
Density LUTs 640 1300 2100 4300 6900
EBR RAM (kbits) 64 64 74 92 240
PLL 1 1 1 2 2
Multi Time Programmable NVCM Yes Yes Yes Yes Yes
1 x SPI controller, 2 x I2C controller Yes Yes Yes Yes Yes
1 x Oscillator, 1 x Timer/Counter Yes Yes Yes Yes Yes
MIPI D-PHY Support Yes Yes Yes Yes Yes
Packages
36-ball WLCSP (0.4, 2.5 x 2.5) 25
49-ball WLCSP (0.4, 3.2 x 3.2) 38
81-ball WLCSP (0.4, 3.8 x 3.8) 60
121-ball fcCSP (0.5, 6 x 6) 100 100 100
256-ball fcCSP (0.5, 9 x 9) 206 206 206 206
324-ball fcCSP (0.5, 10 x 10) 269 269 269
256-ball caBGA (0.8, 14 x 14) 206 206 206 206
324-ball caBGA (0.8, 15 x 15) 269 269 269
400-ball caBGA (0.8, 17 x 17) 325 325

CSI-2 Image Sensor Interfacing

  • Supports CSI-2 High Speed Differential Signaling
    • Both Rx and Tx interfaces
  • From 1-4 lanes of CSI-2 at up to 800 Mbps
  • Can be implemented in a 49 wlcsp (3.2 x 3.2 mm)
  • RAW, YUV or RGB supported

DSI LCD Display Interfacing

  • Supports DSI transmit signaling
    • HS (High Speed) Mode transmit
    • LP (Low Power) Mode transmit and receive
  • Can be implemented in a 49 wlcsp (3.2 x 3.2 mm)
  • Supports DSI formats RGB, YCbCr and User Defined
  • Input bus can also be DSI to enable LCD screen replacement

Microprocessor Interface Expansion

  • Save cost by adding GPIO to low-cost microcontrollers
  • Add additional SPI and I2C interfaces to system control processors
  • Perform voltage level translation with ease
  • Simplify system management with PLD implementation of system status registers

Lattice Diamond Design Software

Leading-edge design software for Lattice FPGA families. Upgrade your design process with an easy-to-use interface, superior design exploration, optimized design flow, Tcl scripting and more. Click here to view more information.

MachXO3 FPGA Family Application Note

  TITLE NUMBER VERSION DATE FORMAT SIZE
Implementing High-Speed Interfaces with MachXO3L Devices TN1281 1.0 12/18/2013 PDF 4.5 MB
MachXO3L Hardware Checklist TN1291 4/23/2014 PDF 283 KB
MachXO3L Programming and Configuration Usage Guide TN1279 1.1 4/12/2014 PDF 1.9 MB
MachXO3L SED Usage Guide TN1292 1.0 4/23/2014 PDF 710.4 KB
MachXO3L sysCLOCK PLL Design and Usage Guide TN1282 1.0 12/18/2013 PDF 4.4 MB
MachXO3L sysIO Usage Guide TN1280 1.0 12/18/2013 PDF 1.9 MB
Using Hardened Control Functions in MachXO3L Devices TN1293 1.0 4/23/2014 PDF 2.9 MB
Using Hardened Control Functions in MachXO3L Devices Reference Guide TN1294 1.0 4/21/2014 PDF 5.7 MB
Using TransFR Technology TN1087 3.5 3/4/2014 PDF 2.4 MB

MachXO3 FPGA Family Data Sheet

  TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO3 256-Pin caBGA Package Migration File 1.0 2/13/2014 CSV 29.9 KB
MachXO3L Family Data Sheet DS1047 2.0 2/25/2014 PDF 2.5 MB
MachXO3L-1300 Pinout 1.0 2/13/2014 CSV 12.3 KB
MachXO3L-2100 Pinout 1.0 2/13/2014 CSV 13.1 KB
MachXO3L-6900 Pinout 1.0 2/13/2014 CSV 19.7 KB
MaxhXO3L-4300 Pinout 1.0 2/13/2014 CSV 15.4 KB

MachXO3 FPGA Family Product Brochure

  TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO3L Product Brief I0238 2/1/2014 PDF 1.1 MB
MIPI Display Serial Interface Solution Product Flyer 12.2 10/22/2013 PDF 1.1 MB

MachXO3 FPGA Family Quality Assurance

  TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO3L Product Family Qualification Summary A 1/29/2014 PDF 327.3 KB

MachXO3 FPGA Family White Paper

  TITLE NUMBER VERSION DATE FORMAT SIZE
Multi-time Programmable ULD FPGAs 1.0 12/1/2013 PDF 163.5 KB

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