For the MachXO2 EFB (Embedded Functional Block) I2C, when is the TRRDY (Transmit Ready) bit of the I2C Status Register (I2C_1_SR register) set to low for I2C master/slave transaction?
The TRRDY goes low in the following cases:
1.
When I2C master is transmitting, the TRRDY goes low whenever you
load the Transmit Register (TXDR) with some data, and at the first
posedge of the SCL for the next frame, it will go high again.
2.
When I2C master is receiving, the TRRDY goes low when you load
the TXDR with the I2C slave address and then goes high at the first posedge
of SCL. Next, the TRRDY will go low as the read bit is detected in the
I2C frame (Repeat Start + Slave address + Read).
When the 8 bits
are successfully received TRRDY goes high. The TRRDY goes low again
when the Wishbone master controller has read the data in the Receive
Register (RXDR).
| Refer to the EFB I2C Master Read-Write waveform in TN1246, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide. |
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