Solution:
To constraint the clock to output delay between a data output and a clock output, use CLOCK_TO_OUT preference with a CLKPORT option.
The CLKPORT option provides the ability to compare DATA and CLK output lines. A CLOCK_TO_OUT (without CLKPORT option) is simply the delay of the clock net plus register to DATA output pin.
To create a CLOCK_TO_OUT relationship between a DATA output pin and a CLOCK output pin, define CLKPORT to compare between two output pins.
For details on CLOCK_TO_OUT preference, refer to Lattice Diamond Help.
User Guides -> Applying Design Constraints -> Setting Preferences -> Setting Timing Preferences -> Setting INPUT_SETUP and CLOCK_TO_OUT preferences.