Article Details

ID: 2296
Case Type: faq
Category: Lattice IP/Reference Design
Related To: DDR2 SDRAM Controller
Family: LatticeECP3

Search Answer Database

Search Text Image

Modelsim:  Why ModelSim report port mismatch during simulation? This occurs after generating the DDR2 IP by typing the file name ddr2 in IPexpress?The error message below is generated by ModelSim:# ** Warning: (vsim-3017) ../../../models/mem/ddr2_db_width_8.v(84): [TFMPC] - Too few port connections. Expected 30, found 15.# Region: /test_mem_ctrl/U1_ddr2_db_width_8/cs[0]/cs_mem0# ** Error: (vsim-3063) ../../../models/mem/ddr2_db_width_8.v(84): Port 'dq' not found in the connected module (1st connection).

The
root cause of the simulation issue is that the file name in IPexpress (which is also the name of the IP's top module)
is the same as the name of the simulation model of the DDR2 memory. 

So with two modules having the same name, only the module compiled later is loaded into the simulation library. When the simulation tool cannot find the library for the module compiled earlier, the mismatch error occurs. 

To avoid this, the file entered in IPexpress should be renamed. This also applies to other IPs such as DDR and DDR3, which have simulation models.