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ID: 1920
Case Type: faq
Category: Implementation
Related To: Constraint-Pref Editor
Family: All FPGA

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Should I generate the positive and negative sides for a differential signal in design and then directly assign them to two pads in a pair ?

In Spreadsheet View, you can define the differential signal to be LVDS I/O type, then assign the signal (i.e, the positive side) to a true pad. The software ispLEVER or Lattice Diamond will automatically assign its negative side to the complementary pad. You can view the results in the PAD specification file.