Article Details

ID: 1920
Case Type: faq
Category: Implementation
Related To: Constraint-Pref Editor
Family: All FPGA

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Radiant, Diamond, and ispLEVER: How should users generate the positive and negative sides for a differential signal in their design?

In Spreadsheet View, users can define the differential signal as LVDS I/O type, then assign the signal (i.e., the positive side) to a true pad.

The software ispLEVER or Lattice Diamond or Lattice Radiant will automatically assign its negative side to the complementary pad. User can view the results in the PAD specification file.