CTimers are built in the CPLD, these range from 32uSec to 2 seconds. The CPLD supports 3 timers, Timer1-3. Timer4 of the CPLD is dedicated to clock the FPGA timers, labeled FTimer. The FTimers are clocked with this slow clock from OUT16.
PAC-Designer software automatically calculates the settings for Timer4, based on the time delays needed on the FTimers.
http://www.latticesemi.com/documents/RD1079.pdf