SPI Slave Peripheral using Embedded Function Block

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Reference Design LogoThe SPI (Serial Peripheral Interface) bus is a synchronous serial data link standard, invented by Motorola that operates in full duplex mode. Multiple slave devices are allowed with unique chip select lines. The XO2 EFB contains a SPI controller that can be configured as a SPI Master or SPI Slave.

This reference design provides a ready to use RTL code segment that implements intuitive interface between:

  • An external SPI master and the XO2 internal registers (user logic)
  • An external SPI master and memory extension in XO2

    The SPI interface is used in master/slave mode where the master device initiates the communication. A typical application of this design would be to provide GPIO expansion to an SPI compliant micro-controller master or interfacing the SPI micro-controller to the Embedded Block RAM (EBR) in the XO2.


    • Ready to use RTL code
    • Prevents user from learning I2C and Wishbone Protocol; Shortens Development Time
    • Programmable Slave Interrupts

    Jump to

    Block Diagram

    Performance and Size

    Tested Devices1 Language fmax I/O Pins Utilization Architectural
    LCMXO2-1200ZE-3MG132C Verilog >50MHz 102 246 LUTs EFB 1.0

    1. May work in other devices as well.
    2. Performance and utilization characteristics generated using the specified test device and Lattice Diamond™ 1.4 software.

    Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


    Technical Resources
    Select All
    SPI Slave Peripheral Using the Embedded Function Block
    RD1125 1.3 1/1/2015 PDF 1.2 MB
    SPI Slave Peripheral Using the Embedded Function Block Reference Design
    RD1125 1.3 1/1/2015 ZIP 730.6 KB

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