In applications where single-ended LVTTL/LVCMOS clock source and ultra-low jitter is required, the ispClock5400D family CleanClock PLL and FlexiClock output blocks provide a robust solution. This document discusses the steps necessary to generate a single-ended clock source from an ispClock5400D device that will meet VOH and VOL requirements across various load conditions.
This reference design demonstrates I/O logic signal standard setup, PLL setup, and how to configure the I2C bus interface of the ispClock5400D device.