Single-Ended Clock from ispClock Differential Clock

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Reference Design LogoIn applications where single-ended LVTTL/LVCMOS clock source and ultra-low jitter is required, the ispClock5400D family CleanClock PLL and FlexiClock output blocks provide a robust solution. This document discusses the steps necessary to generate a single-ended clock source from an ispClock5400D device that will meet VOH and VOL requirements across various load conditions.

This reference design demonstrates I/O logic signal standard setup, PLL setup, and how to configure the I2C bus interface of the ispClock5400D device.


  • Low-jitter LVTTL/LVCMOS single-ended clock source
  • Zero-delay clock buffer
  • Programmable time and phase skew
  • Dynamic device control through I2C

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Block Diagram

Performance and Size

Tested Devices* I/Os I2C Blocks PLLs Revision
ispClock5406D or ispClock5410D 9 1 1 1.0

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


Technical Resources
Generating a Single-Ended Clock Source from ispClock5400D Differential Clock Buffers Reference Design - Documentation
RD1069 1.0 1/22/2010 PDF 171.3 KB
Generating a Single-Ended Clock Source from ispClock5400D Differential Clock Buffers - Source Code
RD1069 1.0 1/22/2010 ZIP 129.9 KB

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