CANmodule-III is a full functional CAN controller module that supports the concept of mailboxes. It is compliant to the international CAN standard defined in ISO 11898-1.

It contains 16 receive buffers, each one with its own message filter, and 8 transmit buffers with prioritized arbitration scheme. For optimal support of Higher Layer Protocols (HLP) such as DeviceNet or SDC, the message filter covers the first two data bytes as well.

The design is written in technology independent HDL and can be mapped to ASIC and FPGA architectures and makes use of on-chip SRAM structures. An AMBA 2 Advanced Peripheral Bus (APB) interface enables smooth integration into ARM based SOC’s. This full synchronous bus interface can easily be connected to other system buses.


  • Standard Compliant
    • Full CAN 2.0A/B compliant
    • Conforms to ISO 11898-1
    • Maximum baudrate of 1 Mbps with 8 MHz system clock
  • Receive Path
    • 16 receive buffers
    • Each buffer has its own message filter
    • Message filter covers: ID, IDE, RTR, Data byte 1 and Data byte 2
    • Message buffers can be linked together to build a bigger message array
    • Automatic remote transmission request (RTR) response handler with optional generation of RTR interrupt
  • Transmit Path
    • 8 Tx message holding registers with programmable priority arbitration
    • Message abort command
    • Single-shot transmission (no automatic retransmission upon error or arbitration loss)
  • System Bus Interface
    • AMBA 2 Advanced Peripheral Bus (APB) Interface
    • Optional: AMBA Advanced High-performance (AHB) Interface
    • Full synchronous zero wait-states interface
    • Status and configuration interface
  • Programmable Interrupt Controller
    • Local interrupt controller covering message and CAN error sources
  • Test and Debugging Support
    • Listen only mode
    • Internal loopback mode
    • External loopback mode
    • SRAM test mode
  • SRAM Based Message Buffers
    • Optimized for low gate-count implementation
    • Single port, synchronous memory based
    • 100% Synchronous Design


  • Transportation
  • Avionics and aerospace
  • Building automation
  • Machine control
  • Medical devices
  • Construction machines
  • Agriculture equipment

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Block Diagram

Performance and Size

The following are typical performance and utilization results.

Lattice Device Comb Seq Mem Clock
iCE65L08-L 1835 1030 6 10 MHz
iCE65L08-T 1839 1030 6 16 MHz
iCE40LP8K 1842 1030 6 28 MHz
iCE40LX8K 1842 1030 6 36 MHz

Ordering Information

This IP core is supported and sold by INICORE, contact INICORE at or visit their website at for more information.