Description:
This is due to a missing GSR instantiation. It is recommended to instantiate GSR on the testbench top-level unit (i.e. tb_top.v).
Solution:
For VHDL:
Right below of the Architecture block, add the instantiation of GSR primitive as shown in the example below:
Architecture Testbench of TOP is
component GSR is
generic (SYNCMODE : string);
port( GSR_N : in std_logic; CLK : in std_logic);
end component;
begin
GSR_INST : GSR
generic map (SYNCMODE => "SYNC")
port map ( GSR_N => '1', CLK => OSC);
.
.
For Verilog:
GSR # (.SYNCMODE ("SYNC"))
GSR_INST (.GSR_N (1'b1), .CLK (OSC));