The APB to AHB-Lite Bridge Reference Design provides an interface between the low power APB and the high-speed AHB-Lite. The design is implemented in Verilog HDL and comes in an IPK format that can be installed with Lattice Propel™ Builder Software as an IP. Implementation is done within Lattice Diamond® software.
This Reference Design is used for interfacing one APB Master and one AHB-Lite Slave. This bridge has two sections: the APB Slave section, and the AHB-Lite Master section. An FPGA fabric-based APB Master is required to use this bridge. When interfacing to multiple AHB-Lite Slaves, this IP should be used together with an AHB-Lite interconnect. The read and write transfers on the APB side are converted into equivalent transfers on the AHB-Lite side. For read and write access, the bridge may add wait states. This is due to the output register in both the AHB-Lite side and the APB side.
User-Configurable Attributes – The attribute values are specified using the IP core Configuration user interface in the Propel Builder software.