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Accelerate Your FPGA Design Cycles with Lattice Macro Design Flow

Accelerate Your FPGA Design Cycles with Lattice Macro Design Flow Blog
Posted 06/29/2023 by Phil Simpson, Director, Tools Marketing at Lattice Semiconductor

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As FPGA devices have expanded in both their density and complexity, design teams are choosing to migrate design principles previously handled by other types of semiconductors – like ASICs and MCUs – to these more sophisticated FPGAs. However, as is often the case, increased complexity can bring to light new challenges, and designers rely on software tools to efficiently implement designs that maximize the advanced capabilities of the FPGA devices.

Lattice Radiant® software offers FPGA design flow features to meet these design principles while capitalizing on the benefits that a FPGA design flow provides – offering best in class tools and features to help users develop their FPGA applications efficiently and effectively.

With the latest Radiant software release, Lattice added macro design flow to enable a block-based design flow. This helps designers achieve faster timing closure, design reuse across different projects, and brings a new level of capability to the existing team-based design environment that the Radiant software supports.

Faster Timing Closure

One of the many benefits that the macro design flow brings is that it can help shorten the timing closure cycle by locking down the performance of the critical design block(s) in the project and only recompiling the other blocks in the design.

Take the example design below.

Accelerate Your FPGA Design Cycles with Lattice Macro Design Flow Blog - Figure 1
Figure 1.

The ‘Filter’ hierarchy is the timing critical block in the design and the rest of the design can close timing relatively easily. The hierarchy ‘Filter’ can be set as a macro. It is recommended that the inputs and outputs of the macro ‘Filter’ are registered at the Register Transfer Level (RTL) level.

This will limit the possibility of the critical paths in the design being between the macro and other parts of the design to which it interfaces. Once timing closure is achieved on the ‘Filter’ design block, it is possible to lock in the performance on the block by setting the macro to preservation level post-place and route. The rest of the design logic placement will be optimized around the macro block.

If there is a change in any of the other design blocks, such as ‘Control’, there will not be a timing closure problem on the block ‘Filter’ as it is locked down.

Design Reuse Across FPGA projects

With the macro design flow, engineers can reuse design blocks to reduce engineering effort, which can result in faster time to market and reduced development costs.

A prime candidate for design reuse is often the next version of the product with a variation of the previous design version. The use of macros can extend design reuse beyond the RTL level to provide productivity benefits in 2 main scenarios:

  1. User has a critical design block that is difficult to achieve timing closure and will be used in multiple other designs/projects targeting the same device. After closing timing on the design block, preferably with 15% to 20% margin, the user can export the macro with locked placement or locked placement and routing for use in other designs targeting the same FPGA device. This provides the benefit of a shorter design cycle by reusing a timing closed block in other designs.
  2. There are multiple versions of a design that will target the same board, e.g., the same board is used in multiple versions of the product with different bitstreams. The pinout and logic interfacing to the device pins, i.e., the design periphery, can be exported as a macro and reused in other projects targeting the same board, guaranteeing performance of the design periphery.

Enabling Parallel Design Development with Team Based Design

Lastly, adding the macro design flow can benefit the overall development process by enabling a ‘team based’ approach. It is common design practice for multiple engineers to work on a single FPGA design. Most commonly, but not exclusively, for designs of 100k Logic Elements or more. The design will be partitioned along the functional boundaries where users have expertise.

For example, if we consider the hierarchy in Figure 1, one designer will work on the ‘Filter’ design block, another designer on the ‘Control’ design block, and another designer on the ‘Transposer’ design block. There will also be an engineer responsible for the integration of the design blocks into the complete design, which has the design block ‘Top’.

This is achieved by partitioning the design at the RTL level to enable parallel development of the design blocks. Each designer is assigned a timing budget and the interfaces between the blocks is defined prior to starting development.

This approach can be extended to the physical design or implementation on the FPGA to further reduce development time. To achieve this, the system integrator will partition the design at both the logical and physical level between the multiple designers and assign an area of the device and timing budget to each designer.

Each designer develops their design and compiles their design within the boundary of their physical region assignment. This can be done in a standalone project using the region and timing constraints assigned by the system integrator. Once the design block is functionally correct and closes timing, ideally with 15 to 20% timing margin, the user will export the design block as a hard macro for integration into the final project with the other designers’ exported hard macro blocks. The system integrator performs final integration and timing closure with all the blocks from the designers. It is recommended that each design block has 15 to 20% timing margin to compensate for any timing degradation that may occur after integration into the final project.

Getting Started with Lattice Macro Design Flow

The Lattice macro design flow is designed to help our customers accelerate time to market, reduce development costs, and simplify their design flow. We plan to add further enhancements in future releases of our Radiant software as we continue finding more ways to address the unique requirements of secure and safety critical applications within Industrial, Automotive, Aerospace and Defense market segments.

To learn more about how Lattice macro design flow can accelerate your FPGA design cycle, reach out to speak with our team, and download the latest Lattice Radiant software to start designing your applications better, faster, and easier. Get a sneak peek of the tool by watching our video.