Human Face Identification Reference Design

Lattice sensAI Reference Design

This reference design implements Convolutional Neural Network(CNN) based human face identification application on a low power Lattice FPGA using an image sensor. The training process is completed on a GPU-powered machine to sharpen the CNN to detect points of reference on a human face and measure them to distinguish the differences between people. This design can be used for identification of other objects by modifying the training database.

The hardware-based reference design includes an SPI, DDR memory interface blocks, an image signal processing engine, eight CNN acceleration engines, and a counting and overlay engine to show registration and identification results.

When the design is deployed on the FPGA, a person can register their face during the registration phase, using 256 different 16-bit values representing distinguishing facial characterizes are extracted and stored. In the identification phase, a registered person’ face can be identified using the hardware 256 16-bit values are extracted and compared to the stored list of values for verification.

Features

  • VGG8 like – 8x (Convolution, Batch Normalization) + 4x Pooling + 1 fully connected CNN
  • Network is trained with around 1 million images including augmentation for various conditions
  • Performance of up to 30 frames per second
  • Power consumption: 850 mW on ECP5 85K s and 200mW on CrossLink-NX 40K

Jump to

Block Diagram

Documentation

Quick Reference
Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
ECP5 Face Identification Quick Start Guide
FPGA-AN-02010 1.0 11/1/2019 PDF 1.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
CrossLink-NX QVGA Mobilenet Human Identification on VVML Board - Project Files
1.0 11/10/2021 ZIP 15.5 MB
Human Face Identification Using CNN Accelerator IP - Project Files
1.0 9/9/2019 ZIP 147.3 MB
CrossLink-NX QVGA Mobilenet Human Identification on VVML Board - Documentation
FPGA-RD-02244 1.0 11/10/2021 PDF 3.3 MB
Human Face Identification Using CNN Accelerator IP - Documentation
FPGA-RD-02062 1.0 9/9/2019 PDF 4.8 MB

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