PCI Express Endpoint Core

Endpoint Solution from SERDES Interface to Transaction Layer

IP ExpressPCI Express is a high performance, fully scalable, well defined standard for a wide variety of computing and communications platforms. It has been defined to provide software compatibility with existing PCI drivers and operating systems. Being a packet based serial technology, PCI Express greatly reduces the number of required pins and simplifies board routing and manufacturing. PCI Express is a point-to-point technology, as opposed to the multidrop bus in PCI. Each PCI Express device has the advantage of full duplex communication with its link partner to greatly increase overall system bandwidth. The basic data rate for a single lane is double that of the 32 bit/33 MHz PCI bus. A four lane link has eight times the data rate in each direction of a conventional bus.


Top Level IP Support

  • 250 MHz Reference Clock Input
  • 125 MHz, 16-bit Data Path User Interface
  • Creates TLPs without ECRC or Sequence Number during Transmit
  • Receives Valid TLPs without Sequence Number during Receive
  • Credit Interface for Transmit and Receive and for PH, PD, NPH, NPD, CPLH, CPLD Credit Types
  • Higher Layer Control for Link Training and Status State Machine (LTSSM) via Ports
  • Access to Select Configuration Space Information via Ports
  • Compliant to PCI-SIG PCI Express 1.1 Base Specifications
  • Jungo Windows/Linux driver support

Configuration Space Support

  • PCI-Compatible Type0 Configuration Space Registers
  • Power Management Capability Structure Registers
  • MSI Capability Structure Registers
  • PCI Express Capability Structure Registers
  • Extend Capabilities Register for Virtual Channel Support


  • Supports all types of TLPs (Memory, I/O, Configuration, and Message)
  • Virtual Channel (VC) Support of 1-8 Channels
  • Flow Control Enforcement with Separate Credit Interface per VC
  • Optional ECRC Generation/Checking
  • Power Management User Interface

Data Link Layer

  • Data Link Control and Management State Machine
  • Flow Control Initialization
  • Ack/Nak DLLP Generation/Termination
  • Power Management DLLP Generation/Termination through simple user interface
  • LCRC Generation/Checking
  • Sequence Number Appending/Checking/Removing
  • Retry Buffer and Retry Management
  • Credit Availability Calculation and Reporting

PHY Layer

  • 2.5 Gbps Electrical Interface
  • Serialization and De-serialization (SerDes)
  • 8b/10b Symbol Encoding/Decoding
  • Link State Machine for Symbol Alignment
  • Clock Tolerance Compensation supports +/- 300 ppm
  • Framing and Application of Symbols to Lanes
  • Data Scrambling
  • Link Training and Status State Machine (LTSSM)
    • Electrical Idle Generation
    • Receiver Detection
    • TS1/TS2 Generation/Detection
    • Land Polarity Inversion
    • Higher Layer Control to jump to Define States

Jump to

Block Diagram

Performance and Size

PCI Express IP Configuration
x4 Native X1 Native X2 Downgraded
FPGA Families Supported LatticeECP3 and ECP5
Minimal Device Needed LFE317E-7FN484C LFE5UM-45F-7BG756CES LFE3-17E-7FN484C LFE5UM-25F-7BG381C LFE317E-7FN484C LFE5UM-45F-7BG756CES
Targeted Device LFE395E-7FPBGA1156C LFE5UM-85F-7BG756CES LFE3-95E-7FPBGA1156C LFE5UM-85F-7BG756CES LFE395E-7FPBGA1156C LFE5UM-85F-7BG756CES
Data Path Width 64 64 16 16 64 64
LUTs 12200 13900 6040 6207 12900 12200
sysMEMTM EBRs 11 11 4 4 11 11
Registers 9746 9763 4027 4188 8899 9746
PCI Express 5G IP Configuration
x2 Native X1 Downgraded
FPGA Families Supported Lattice ECP5-5G
Targeted Device LFE5UM5G-85F-8BG756C LFE5UM5G-85F-8BG756C
Data Path Width 64 64
LUTs 13626 13073
sysMEMTM EBRs 7 7
Registers 9968 8892

Ordering Information

Family Lanes License Type Part Number
CertusPro-NX x1 Native Single-Design PCI-EXP1-CPNX-U
x2 Native Single-Design PCI-EXP2-CPNX-U
x4 Native Single-Design PCI-EXP4-CPNX-U
Certus-NX x1 Native Single-Design PCI-EXP1-CTNX-U
CrossLink-NX x1 Native Single-Design PCI-EXP1-CNX-U
Multi-Site PCI-EXP1-CNX-UT
ECP5-5G x2 Native Single-Design PCI-EXP2-E5G-U
Multi-Site PCI-EXP2-E5G-UT
ECP5 x4 Native Single-Design PCI-EXP4-E5-U
Multi-Site PCI-EXP4-E5-UT
x1 Native Single-Design PCI-EXP1-E5-U
Multi-Site PCI-EXP1-E5-UT
LatticeECP3 x4 Native Single-Design PCI-EXP4-E3-U3
Multi-Site PCI-EXP4-E3-UT3
x1 Native Single-Design PCI-EXP1-E3-U3
Multi-Site PCI-EXP1-E3-UT3
LatticeECP2M x1 Native Single-Design PCI-EXP1-PM-U3
x4 Native Single-Design PCI-EXP4-PM-U3
Multi-Site PCI-EXP4-PM-UT3

Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.

To find out how to evaluate or purchase the PCI Express x1 Endpoint IP core, please contact your local Lattice Sales Office.


Quick Reference
ECP5 and ECP5-5G PCI Express Soft IP Ease of Use Guidelines
FPGA-TN-02045 1.1 11/20/2019 PDF 917.3 KB
ECP5 and ECP5-5G PCI Express Soft IP Ease of Use Guidelines
FPGA-TN-02045 1.1 11/20/2019 PDF 917.3 KB
PCIE X4 IP Core - Lattice Radiant Sofware
FPGA-IPUG-02126 1.0 6/23/2021 PDF 3.6 MB
PCI Express x1/x2/x4 Endpoint IP Core User Guide - Lattice Diamond Software
FPGA-IPUG-02009 2.0 10/2/2020 PDF 3.6 MB
PCIe Endpoint IP Core - Lattice Radiant Software
FPGA-IPUG-02091 1.4 10/4/2021 PDF 4.4 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.