PCI Express Endpoint Core

Endpoint Solution from SERDES Interface to Transaction Layer

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PCI Express is a high performance, fully scalable, well defined standard for a wide variety of computing and communications platforms. It has been defined to provide software compatibility with existing PCI drivers and operating systems. Being a packet based serial technology, PCI Express greatly reduces the number of required pins and simplifies board routing and manufacturing. PCI Express is a point-to-point technology, as opposed to the multidrop bus in PCI. Each PCI Express device has the advantage of full duplex communication with its link partner to greatly increase overall system bandwidth. The basic data rate for a single lane is double that of the 32 bit/33 MHz PCI bus. A four lane link has eight times the data rate in each direction of a conventional bus.

Features

  • PCI Express 2.0 electrical compliance
  • MSI Capability Structure Registers contained inside the core
  • Supports all types of TLPs (memory, I/O, configuration and message)
  • 128, 256, 512, 1 k, 2 k, or 4 Kbyte maximum payload size
  • 125 MHz user interface
    For 2.5G IP core:
    • Native x4 and Downgraded x1/x2 support a 64-bit datapath
    • Native x1 supports a 16-bit datapath
    For 5G IP core:
    • Native x2 and Downgraded x1 support a 64-bit datapath

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Block Diagram

PCI Express 1X Endpoint CoreExpand Image

Performance and Size

PCI Express IP Configuration

x4 Native X1 Native X2 Downgraded
FPGA Families Supported LatticeECP3 and ECP5
Targeted Device LFE3 LFE5UM LFE3-95E LFE5UM LFE3-95E LFE5UM
Data Path Width (Core Data Width)
 64 64 16 16 64 64
LUTs 12200 13900 6040 6207 12900 12200
sysMEMTM EBRs 11 11 4 4 11 11
Registers 9746 9763 4027 4188 8899 9746
PCI Express 5G IP Configuration

x2 Native X1 Downgraded
FPGA Families Supported Lattice ECP5-5G
Targeted Device LFE5UM5G LFE5UM5G
Data Path Width (Core Data Width)
 64 64
LUTs 15673 13893
sysMEMTM EBRs 7 7
Registers 11249
 9660

Ordering Information

Device Family Partner Number
Single Design Multi-Site Subscription
LatticeECP5-5G PCI-EXP2-E5G-U PCI-EXP2-E5G-UT PCI-EXP2-E5G-US
LatticeECP5 PCI-EXP4-E5-U PCI-EXP4-E5-UT PCI-EXP4-E5-US
PCI-EXP1-E5-U PCI-EXP1-E5-UT PCI-EXP1-E5-US
LatticeECP3 PCI-EXP4-E3-U3 PCI-EXP4-E3-UT3 PCI-EXP4-E3-US
PCI-EXP1-E3-U3 PCI-EXP1-E3-UT3 PCI-EXP1-E3-US
LatticeECP2M PCI-EXP1-PM-U3 N/A N/A
PCI-EXP4-PM-U3 PCI-EXP4-PM-UT3 N/A

Evaluate: To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the PCI Express Endpoint IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
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ECP5 and ECP5-5G PCI Express Soft IP Ease of Use Guidelines
FPGA-TN-02045 1.2 1/24/2022 PDF 918.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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ECP5 and ECP5-5G PCI Express Soft IP Ease of Use Guidelines
FPGA-TN-02045 1.2 1/24/2022 PDF 918.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
PCIE X4 IP Core - Lattice Radiant Software
FPGA-IPUG-02126 1.2 4/6/2023 PDF 3.2 MB
PCI Express x1/x2/x4 Endpoint IP Core User Guide - Lattice Diamond Software
FPGA-IPUG-02009 2.0 10/2/2020 PDF 3.6 MB
PCIe Endpoint IP Core - Lattice Radiant Software
FPGA-IPUG-02091 1.4 10/4/2021 PDF 4.4 MB

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