The Lattice 2.5G Ethernet MAC + PHY IP core implements the Media Access Controller (MAC) and state machine functions for the Physical Coding Sub-layer (PCS) described in the IEEE 802.3 (1000BASE-X) specification. Note that the IEEE specification describes a PCS that operates at 1 Gbps. Therefore, this 2.5G PCS state machine does not conform to the IEEE standard specification. The two major differences are data rate (2.5 Gbps instead of 1 Gbps) and 16-bits GMII data bus width.
Resource Utilization details are available in the IP Core User Guide.
Features
- Compliant to IEEE 802.3-2005 standard
- Full-duplex operation
- Independent TX and RX Maximum Transmission Unit (MTU) frame length
- Programmable promiscuous (transparent) mode
- Supports deficit idle count (DIC)
