Sign In         see this page in JapaneseKorean language homepageChinese language homepage

QDR Memory Controller

Lattice Reference DesignsQDR SRAM is a new memory technology defined by a number of leading memory venders for high-performance and high-bandwidth communication applications. QDR is a synchronous pipelined burst SRAM with two separate unidirectional data buses dedicated for read and write operations running at double data rate. This reference design utilizes the ORCA� Series 4 library elements IODDR and HIODDR to create 178MHz double data rate read/write access to the QDR memory and targets for ORCA 4 FPGA and FPSC devices.

QDR Memory Controller

 

Family Tested Device* PLL Usage PFU Usage(include pipeline module) Registers Usage Max. Freq.
ORCA4 FPSC ORSPI4-2FE1036C 2 75 out of 2024 643(includes 360 registers for pipeline module) 178 MHz
LatticeEC LFEC20E-4F672C 2 75 out of 2464 613(includes 360 registers for pipeline module) 192 MHz
LatticeXP LFX10C-4f388C 2 71 out of 1216 612 (includes 360 registers for pipeline module) 178 MHz

PDF file download design documentation

 

EXE files download source code

 

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.