Answer Database

Have a question? We've got the answer.

Narrow Your Results

Family
Article Type
Category
Type of Issue
Documentation (48)
Hardware (759)
IP/Reference Design (162)
Software (572)
Related To
Topic ID Family Article Type Category Related To
For the POWR1220AT8 device, can we switch between I2C and Closed Loop Trim mode... 2891 Power Manager II faq PAC-Designer TRIM Usage
Why do we see glitches in functional simulation, but not in timing simulations for an... 2530 LatticeECP3 faq Simulation Aldec
Why does LatticeECP3 Generic DDR (Double Data Rate) design generates missing attribute... 2519 LatticeECP3 faq Architecture Generic DDR
Why is the SVF file generated from ispVM on a SSPI interface programming doesn\'t match... 2512 MachXO2 faq Device Programming Embedded Programming
Why I am not able to use Toggle breakpoint in Aldec Active-HDL Lattice Edition II ? 2468 All Devices faq Simulation Aldec
How can I add Bus Tap in schematic ? 2461 All FPGA faq Implementation Schematic
What is the status of LatticeXP2\'s INITN and DONE pin during and after configuration?... 2445 LatticeXP2 faq Device Programming Configuration\/Programming
The Spreadsheet View has a MaxSkew column. Is this the same as applying a MAXSKEW... 2443 All FPGA faq Implementation Constraint-Pref Editor
How to determine the size of PROM and scratchpad memories of Lattice Mico8 from the... 2344 All Devices faq Lattice IP\/Reference Design Mico8 Microcontroller
What is the correct slave address of Lattice MachXO2 EFB I2C component? 2343 MachXO2 faq Architecture I2C
How can I update the software code generated by the Mico System Builder (MSB) in my... 2341 All Devices faq Implementation Mico32(MSB)
What kind of the speed grade does the LatticeMachXO2 support? How about the performance... 2336 MachXO2 faq Architecture General Logic
Do we need to connect txiclk_ch[n] pins when FPGA FIFO bridge is bypassed?DUPLICATE FAQ... 2335 LatticeECP3 faq Architecture SERDES\/PCS
When will Native Generic Object (NGO) file be generated, and how is it utilized? 2332 All FPGA faq Implementation Other
Thus we generate an output clock which is non-integer multiple of input frequency by... 2315 MachXO2 faq Architecture PLL\/DLL\/Clock Routing
How to access the TraceID register for LatticeMachXO2 device? 2314 MachXO2 faq Architecture Configuration\/Programming
In LatticeMachXO2 devices, Are external 100 ohm resister to terminate an LVDS receive... 2311 MachXO2 faq Architecture IO
What is Additive latency (AL) and how to use\/set the AL timing parameter for the DDR2... 2308 LatticeECP3 faq Lattice IP\/Reference Design DDR2 SDRAM Controller
Why I cannot start the debug session using Reveal Logic Analyzer after I re-compile... 2299 LatticeXP2 faq Debugging Reveal
How to access the memory mapped address locations of the Lattice Mico System in my C code? 2270 All Devices faq Implementation Mico32(MSB)