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  • All Devices: Do the IEEE VHDL library packages (eg., IEEE.std_logic_1164 and IEEE.numeric_std)…
    7291
    All Devices
    Other
  • All Devices: How to properly Configure FPGA with on-board programmer using HW-USBN-2A/B?
    7204
    All FPGA
    Programming and Configuration
  • How do I preserve the components of my design for both Radiant and Diamond? How do I prevent…
    7205
    All FPGA
    Diamond
  • ispLever Clasic 2.1 and below: How to avoid optimization of unconnected pins in a schematic entry on…
    7207
    ispMACH 4000
    ISPLever/ISPLeverClassic
  • PCIe for Nexus FPGAs: What is the size of the Transmit Buffer and Receive Buffer in PCIe X1 IP Core…
    7206
    Certus-NX
    PCIe
  • Synthesis Error for SystemVerilog design: "Error: No definition for function
    7200
    All FPGA
  • Lattice ECP5 : What is the VSSIO used for in the pinout file of ECP5?
    7248
    LatticeECP5
    Fabric
  • Lattice Radiant: Why do users cannot select the CFG2 address for Dual-boot implementation in…
    7243
    MACHXO5
  • Radiant: How to initialize register values when using LSE synthesis tool?
    7241
    All FPGA
    Radiant
  • Radiant versions 2023.1 and newer: Why is there a MAP DRC update on 2023.1 and newer versions of…
    7242
    CrossLink-NX
    Radiant
  • Propel: Why is my Linker Script Section Name unable to map to the instantiated memory region?
    7249
    All FPGA
    Propel (RISC-V)
  • Lattice Propel: Why am I unable to view my custom Memory in the Data Memory Region of Linker…
    7229
    All FPGA
    Propel (RISC-V)
  • Radiant 2023.2 SP1: Why does Lattice PCIe X4 IP v2.3.1 ModelSim simulation using Radiant 2023.2 SP1…
    7223
    CertusPro-NX
    PCIe
  • How do you view or print a waveform with ModelSim using the VCD file generated by Reveal Analyzer?
    7227
    All Devices
    Diamond
  • Synplify Pro on Diamond version 3.13 and older: evaluation of mixed real-integer expressions is…
    7226
    All FPGA
    Diamond
  • Lattice Propel: Why is my Propel Builder soft IP not available/missing in IP Catalog?
    7230
    All FPGA
    Propel (RISC-V)
  • Radiant 2023.1: Why is the 'create_clock' constraint excluded from FDC?
    7236
    CertusPro-NX
    Radiant
  • Lattice Radiant: What does this warning mean "Generated_clock: not connect to any master clock…
    7235
    CertusPro-NX
  • PCIe for Nexus FPGAs: Why is PCIe IP downgraded to x1 lane even though it is configured as x1 lane?
    7234
    CertusPro-NX
    PCIe
  • Where to check the list of supported SPI Flash?
    7233
    All FPGA
    Programming and Configuration
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