Lattice Diamond Design Software

Lattice Diamond Software

FPGA Design, Meet Easy.

Exploring Design Alternatives Made Easy – Finding the best solutions for smaller devices often requires evaluating multiple solutions. Lattice Diamond allows easy exploration of alternate solutions without resorting to workarounds.

Easy to Use in Many Ways – Adapting to a new tool is hard. Lattice Diamond makes this easier by adapting to your style of working and by providing tools that make common tasks easier. No matter how you like to work, Lattice Diamond can adapt to your style.

Design Flow Tailored for Lattice Devices – Applications that use low-density and ultra low-density FPGAs require flexibility, verification, and the ability to iterate quickly. Lattice Diamond does this and more.

Testing 4

Exploring Design Alternatives Made Easy

Finding the best solutions for smaller FPGAs often requires evaluating multiple alternatives. Lattice Diamond allows easy exploration of alternate solutions without resorting to workarounds like multiple projects or different revisions. Diamond provides several unique features that make exploring design alternatives easy:

  • Supports VHDL, Verilog, EDIF, schematics and multiple implementations. One Lattice Diamond project does the work that normally requires multiple projects in other tools.
  • Strategies contain all the tool settings used within an implementation. These are the "recipes" needed to complete your design, and they can be saved and shared easily.
  • Add, change, or remove entire sets of constraints, power voltages, or debug access easily with a mouse click.
  • Utilize Synopsys Synplify Pro or Lattice Synthesis Engine (LSE) to explore additional implementation options for achieving the best results.
  • Run Manager lets you execute implementations in parallel on your multi-core machines to find the best solution faster.

Easy to Use in Many Ways

Adapting to a new tool is hard. No matter how you like to work, Lattice Diamond can adapt to your style. And Lattice Diamond provides tools that make common tasks easier.

  • You can detach tool views to allow you to concentrate on a single tool at time for small monitors or have multiple tool views open if you have multiple monitors.
  • Specific tools have been designed to make common tasks easier. ECO Editor, Programmer, and Reveal are just some examples of tools tailored for making individual tasks easier.

Design Flow Tailored for Lattice Devices

Applications that use low-density and ultra low-density FPGAs require flexibility, verification, and the ability to iterate quickly. Lattice Diamond does this and more.

  • Timing Analysis view saves time by allowing interactive changes to constraints and viewing results without disturbing your design.
  • Simulation Wizard provides easy integration with simulation, even if you aren't a simulation expert.
  • Lattice Diamond has an easy to use GUI, but sometimes a script is the fastest way to do a task. Full Tcl scripting support is provided with interactive help features.

Complete Design Environment

Lattice Diamond contains a complete set of tools for implementing your design. It includes tools for the following areas and third-party tools.

  • Design Entry
  • Synthesis
  • Implementation
  • Analysis
  • On-chip Debug Hardware Analysis
  • Simulation
  • Programming
  • Deployment
  • Synopsys Synplify Pro for Lattice Synthesis
  • Aldec Active-HDL Simulation

Lattice Diamond Key Concepts

Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Lattice Diamond features provide significant improvements and new concepts not found in earlier Lattice design software tools. Primarily among the new features are expanded projects and the new timing analysis flow.

Report View

Improved Projects Enable Design Exploration

Design projects in Lattice Diamond offer an order of magnitude increased functionality by allowing more robust projects and capabilities that allow design exploration. Key improvements to Lattice Diamond projects include the following:

  • Allow the mixing of Verilog, VHDL, EDIF, and schematic sources
  • Through Implementations, allow multiple versions of a design within a single project for easy design exploration
  • Strategies allow implementation “recipes” to be applied to any implementation within a project or shared between projects
  • Manage and choose files for constraints, timing analysis, power calculation, and hardware debug
  • Use Run Manager view to allow parallel processing of multiple implementations in order to explore design alternatives for the best results. Run Manager allows you to selectively choose implementations in your project and compare the results. You can also set how many cores to use for multi-core processors to manage the load on your system.

Implementations

Implementations define the design structural elements for a project. An implementation contains the structure of a design and can be thought of as the source and constraints to create the design. For example, one implementation may use inferred memory and another implementation may use instantiated memory. There can be multiple implementations in a project, but only one implementation can be active at a time and there must be at least one implementation. You can copy an existing implementation by creating a new one and selecting the source of an existing implementation. An Implementation is automatically created whenever you create a new project. Implementations consist of:

  • Input files
  • Constraint files
  • Debug files
  • Script files
  • Analysis files

Strategies

Strategies are all the implementation related tool settings collected in one convenient location. An implementation defines what is in the design, and a strategy defines how that design will be run by the implementation tools (synthesis, translate, map, par, bitgen, etc.). The strategies in a project are automatically shared among all the implementations, and they can be saved and used in multiple projects. The following are key facts to understanding strategies and their role in Lattice Diamond projects.

  • Strategies are basically implementation "recipes".
  • There are four predefined strategies in Lattice Diamond plus customized user strategies.
  • Predefined Strategies cannot be edited, but they can be cloned and then modified and saved as custom user strategies.
  • Custom user strategies can be edited, cloned, set as the active strategy and removed.
  • There can be many strategies in a project, but only one can be active at a time for each implementation and each implementation must have an active strategy.
Timing View

Timing Analysis Flow

The new Timing Analysis view offers an easy to use graphical environment for navigating timing information. Simply click on a constraint and see the timing paths, detailed paths, or path schematic views. Easy visual cues, such as coloring constraints that fail in red, provide instant feedback on your design. A key new benefit in Timing Analysis view is rapidly updated analysis when timing constraints are changed, including clock jitter analysis. No longer must you re-implement your design to re-run a TRACE report. Instead, change a timing constraint, click update in Timing Analysis and your analysis report is directly run. The new flow for using timing analysis in Diamond is as follows:

  • Open Timing Analyzer View which reads constraints the design in memory
  • Save constraints as TPF file
  • Click preferences icon in Timing Analyzer view to edit constraints only for timing analysis
  • Edit constraints in Spreadsheet View, then click the update icon in Timing Analyzer view
  • Repeat as necessary. When complete, copy changed constraints back to the design in memory by selecting the preferences in Spreadsheet View and choose export TPF to LPF.

Lattice Diamond Complete Feature List

Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Lattice Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous additional enhancements. The combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before. Lattice Diamond software is a robust and complete software environment from entering the design to programming your Lattice device. It uses proven implementation engine technology developed for six generations of tools. Below is a list of all the major tool areas provided in the Lattice Diamond software:

Project Management

Features Projects

Lattice Diamond Environment

The Lattice Diamond software environment provides a set of functions including the following tools.

  • File List view for project management
  • Process view for controlling implementation of designs
  • Start page which offers quick links to opening projects, recent projects, software updates, on-line help, and Lattice website
  • Report view which offers a centralized location for viewing all design reports and displays reports from multiple implementations.
  • Centralized location for all outputs, warnings, errors, and scripting control
  • Menus, icons, and controls for all integrated tool views

Robust Project Capabilities

Design projects in Lattice Diamond offer an order of magnitude increased functionality by allowing more robust projects and capabilities that allow design exploration. Key improvements to Lattice Diamond projects include the following.

  • Allow the mixing of Verilog, VHDL, EDIF, and schematic sources
  • Through Implementations, allow multiple versions of a design within a single project for easy design exploration
  • Strategies allow implementation “recipes” to be applied to any implementation within a project or shared between projects
  • Manage and choose files for constraints, timing analysis, power calculation, and hardware debug
  • Use Run Manager view to allow parallel processing of multiple implementations in order to explore design alternatives for the best results. Run Manager allows you to selectively choose implementations in your project and compare the results. Resource usage is also included in the table. And, you can also set how many cores to use for multi-core processors to manage the load on your system.

Design Entry

HDL Entry (Text Editor)

Lattice Diamond includes an intuitive HDL text editor that includes keyword highlight support for: VHDL, Verilog HDL, EDIF, and the Lattice Preference Language. You also set your favorite editor as the default.

Schematic Editor

Schematic Editor view helps you visualize programmable logic designs in a graphical format using block diagrams of HDL blocks or gate-level schematics for all device families.

Features IPexpress

IPexpress

IPexpress view is the interface to the Lattice catalog of functional modules, reference designs, and intellectual property(IP), all optimized for Lattice programmable products. IPexpress helps accelerate the design process by helping you smoothly configure and integrate these functions into your custom design. Lattice IP cores include some of the most popular industry-standard functions such as PCI bus controllers, DDR memory controllers, Ethernet MACs, DSP functions and many more. To learn more about these IP cores, click here.

HDL Analysis

Save time by analyzing your design prior to synthesis with the new integrated HDL code checking capability. The Hierarchy view is automatically opened when the project is opened along with the File list and Process view. Post synthesis, the Hierarchy tab is annotated with the resource utilization to give an idea about the elements used per each level of hierarchy. It is also updated post map with physical (slices) elements. The HDL Diagram tool can be opened from the toolbar or menu. Within HDL Diagram are a number of views for graphically viewing the pre-synthesis HDL source and a number of BKM (Best Known Methods) rule checks can be run against your design.

HDL Diagram

LDC Editor (Constraint editor for LSE)

Users of the Lattice Synthesis Engine (LSE) tool can now create and edit Synopsys Design Compiler (SDC) synthesis constraints in the new Lattice Design Constraints graphical editor. This editor automatically populates design clock, port and net names and provides real time syntax and semantic checks. It generates an SDC file that can be used with LSE.

LDC Editor

Platform Designer

Platform Designer is a new tool that enables you to create and control a complete hardware system using the Platform Manager 2 device or MachXO2 with external analog sense and control (ASC). Platform Designer’s integrated design environment allows you to configure the device, implement the hardware management algorithm, generate the HDL, simulate, assign pins, and finally generate the JEDEC files required to program and configure the device on the circuit board. Platform Designer contains separate editors for configuring global ASC and device settings; current, temperature, and voltage monitors; fan controller and fault logger components; ports and nodes; and logic controls.

Platform Designer

Synthesis

Lattice Synthesis Engine (LSE)

For MachXO2 and MachXO device families the new Lattice Synthesis Engine (LSE) is available for exploring how to achieve the best results. LSE is the result of several years of development initially focused on Lattice's internal FPGA architecture development. LSE supports both Verilog and VHDL languages and uses SDC format for constraints. It is integrated into the Lattice Diamond design software as a synthesis tool choice when a supported device family is selected. More information on LSE is available here.

LSE Diagram

Synopsys Synplify Pro for Lattice

Lattice Diamond includes the industry-leading synthesis solution, Synopsys Synplify Pro for Lattice, with a range of tools and features that help you manage large designs, and extract the very best fit and performance, optimized for Lattice FPGAs. Synplify Pro for Lattice also includes HDL Analyst, which automatically produces an RTL schematic of your design for analysis and cross-probing with RTL source code. Other advanced features include the following.

  • Behavior Extracting Synthesis Technology (BEST) produces globally optimized designs in a fraction of the time required for traditional tools
  • Comprehensive Language Compiler for supporting a wide range of Verilog and VHDL language constructs
  • SCOPE constraints editor for spreadsheet-like entry of design constraints for synthesis, place and route
  • Integrated module generation for high-performing, area-efficient implementation of arithmetic/datapath functions
  • Automatic RAM inferencing for technology independent RTL source code
  • Integrated language-sensitive HDL source code editor with syntax checker
  • Automatic register balancing of pipelined multipliers and ROMs for improved performance
  • Customized mapping software for each FPGA device family ensures optimal implementation in the target device and technology independence
  • HDL Analyst automatically produces an RTL schematic of your design for analysis and cross-probing with RTL source code. Cross-probing is also possible from the timing report (twr) generated by Diamond
  • Mixed Verilog and VHDL support
  • Compile-point support
  • Automatic re-timing (balancing registers across combinatorial logic) for improved performance
  • Automatic gated-clock and generated clock conversion for efficient implementation of RTL written for an ASIC into an FPGA
Synplify Pro

Implementation

Spreadsheet View

Design Planner in ispLEVER incorporated several functions in a separate tool. These functions are now individual views in Lattice Diamond and work seamlessly with the other views. A key component is the Spreadsheet View. This view allows the ability to enter and view design constraints such as pin assignments, clock resource usage, global preferences, timing preferences and more. Spreadsheet View provides cross probing to several other views and works with the File List view for managing multiple constraints files. When migrating to a lower cost device in one of the device families, Spreadsheet View can show the incompatible pins.

Package View

Package View allows easy graphical assignment of signals to pins. Package View also provides a graphical representation of SSO noise analysis to check noise caused by parallel output switching. Package View provides cross probing to several other views including Spreadsheet View, Floorplan View and others. When migrating to a lower cost device in one of the device families, Package View can show the incompatible pins.

Floorplan View, Physical View, Netlist View, NCD View, Device View

Lattice Diamond provides several abstractions for design and device tasks. Floorplan View provides the ability to view and edit placement constraints. Physical View provides a detailed read-only view of the physical routing of paths for more detailed understanding of timing issues. Netlist View provides browsing of design ports, instances, and nets for drag and dropping into other views such as Package View for setting constraints. NCD View provides access to detailed usage information of physical components such as SLICEs, PIOs, IOLOGIC, and other elements. Device View provides the ability to browse device specific resources and cross-probe to other views. Together these views provide access to the information needed to analyze and constrain the design’s implementation.

ECO Editor

ECO Editor provides quick access to commonly used netlist editing functions such as sysIO settings, PLL parameters, and memory initialization without having to use a full editor such as EPIC. Signal Probe capability allows users to easily assign internal signals to external pins for use as test probes.

EPIC

EPIC device editor provides detailed access and editing of the physical implementation of your design. Physical details like route interconnect, physical element programming, and I/O buffer configuration can be examined or directly edited after the PAR process, giving you ultimate control.

Analysis

Timing View

Timing Analyzer View

The new Timing Analysis View offers an easy to use graphical environment for navigating timing information. Click on a constraint and see the timing paths, detailed paths, and path schematic views instantly. Timing Analysis View also includes the same information for unconstrained paths, speeding up your timing closure flow. Easy visual cues, such as coloring constraints that fail in red, provide instant feedback on your design. A key new benefit in Timing Analysis View is rapidly updated analysis when timing constraints are changed, including clock jitter analysis. No longer must you re-implement your design to re-run a TRACE report. Instead, change a timing constraint, click update in Timing Analysis and your analysis report is directly run.

Power Calculator

Power Calculator uses highly accurate data models along with a data driven power model to provide power estimation and calculation results, graphical power displays, and reports. Thermal resistance options can be used to model real world thermal conditions including heatsinks, airflow, and board complexity. The data driven approach of Power Calculator provides very accurate results for both power estimation and calculation giving you high confidence when targeting the specific power budgets of low power design applications. Power Estimation is also available as a standalone application.

On-chip Debug Hardware Analysis

Reveal Inserter

Reveal Inserter uses a signal-centric model that allows easy insertion of embedded logic analyzer debug hardware for real-time analysis. Reveal features the ability to use, multi-event triggering which can be dynamically changed at run-time.

Reveal Analyzer

Reveal Analyzer

Reveal Analyzer features the ability to use, multi-event triggering which can be dynamically changed at run-time and an integrated waveform for displaying captured events from the target FPGA. New in Lattice Diamond is a more streamlined Reveal Analyzer module with multiple cursors and rubber banding for measuring events in the waveform display. And, downloading trace data or setting complex trigger configuration is really fast.

Tcl Scripting Support

Lattice Diamond software adds capabilities for scripting the design flow. In addition to the Tcl console tab in the environment, a separate Tcl console application allows running scripts independently. Lattice Diamond specific Tcl command dictionaries are available for the following areas.

  • Projects management
  • Netlist queries
  • HDL code checking
  • Power calculation
  • On-chip debug insertion
  • On-chip debug analysis

Simulation

Simulation Wizard

Lattice Diamond provides easy export of designs to simulators through the Simulation Wizard, including support for multi-file testbenches. The Simulation Wizard will guide you through all the necessary steps to get your design to a simulator in the format you want it. Simulation Wizard is the easy way to get exactly what you want.

Simulation Wizard

Aldec Active-HDL Lattice Edition II

Lattice Diamond includes the comprehensive and feature-rich simulation environment Active-HDL Lattice Edition II from Aldec. Active-HDL Lattice Edition II features mixed language simulation of VHDL and Verilog, and many advanced verification and debug features such as Language Assistant, Code Execution Tracing, Advanced Breakpoint Management and Memory Viewing. When using Lattice Diamond with the free license, simulation is enabled for Active-HDL Web Edition II which offers many of the same features with less capacity. Aldec Active-HDL Lattice Edition II and Active-HDL Web Edition II are available on Windows platforms only.

Aldec Active-HDL

Programming

Programmer

Fully integrated into Diamond and standalone, Programmer allows easy direct normal programming of single or multiple FPGA devices. Users can also add support for their own SPI Flash devices directly in Programmer, allowing immediate support for these devices.

Deployment tool

Diamond Deployment Tool provides an intuitive wizard approach to create the appropriate device programming file in the format required by your deployment method. It offers functionality such as file conversion, external memory file generation, improved I2C embedded for the MachXO2 family and Slave SPI support for the LatticeECP3 and LatticeXP2 device families. Getting the job done more quickly is the goal of these tools.

Deployment Wizard

Lattice Synthesis Engine (LSE)

Why Synthesis Choice Matters

A single synthesis tool cannot create the best results for all architectures. Differences in the order that optimizations are applied, and differences in the scope of architectures supported can both result in different results. The synthesis step has the most potential to improve the quality of results in FPGA design. Even if timing is met, further optimization in synthesis might enable targeting a lower cost, lower speed-grade FPGA which can save 15%-30% on costs.

Synthesis quality of results (QoR) is affected by the design snapshot after the HDL parsing, the tool flow, and the order in which the optimizations executed. Because of this some tools may perform better on some set of designs than other tools. Having a choice allows a designer to see design performance on different tools with different commercial options before finalizing the design.

LSE Technology

Lattice Synthesis Engine (LSE) is a logic-synthesis tool designed specifically to produce the best possible results for ultra-low density and low density FPGAs. It synthesizes HDL designs to netlist files constructed with Lattice specific primitives. LSE converts description of digital system to the actual high performance circuits of Lattice technology, recognizing and implementing high-level abstract structures like RAMs, ROMs, finite state machines (FSMs), arithmetic operators, and other elements.

The tool is designed to optimize a given RTL design to specific performance goals: Area, Timing or Balanced. The tool optimizes the design according to user design constraints. Constraint entry is enabled and simplified by the graphical user interface (LDC Editor), which extracts and displays all the relevant design information so user can quickly specify accurate design constraints. The constraints convey performance requirements and optimization options to the optimization engines.

After the optimization process is complete, LSE generates a netlist ready for Map, and Place & Route steps of the FPGA design flow. LSE generates the output in ngd format, which is a fully complete netlist (no black boxes). The option of generating an EDIF netlist is also available. LSE is tightly integrated within the Lattice Diamond environment, making it simple and easy to use.

LSE Diagram

LSE Development

LSE has been developed and validated for many years. It was first publically released in Diamond 1.1 on November 8, 2010 as beta for Lattice MachXO & MachXO2 devices. The tool has been continuously tested and refined by the internal QA & Applications, and customers over each subsequent Diamond and iCEcube2 release. Since 2008, LSE has been tested and validated with numerous design suites such as basic logic cases, standard benchmark suites, communication prototypes, board demos and IPs. LSE has shown consistently excellent results on XO/XO2 benchmarking suites. Over the last couple of years multiple field evaluations were launched with LSE to increase customer usage. In the process, many customer designs have been collected, tested and included in Lattice internal benchmarking. Currently more than 20,000 unit test cases are run with LSE to validate QoR and functional verification on weekly basis.

Lattice Synthesis Engine (LSE) Key Features

Operating System Support

  • Windows:
    • Windows XP 32-bit
    • Windows Vista 32-bit
    • Windows 7 32-bit & 64-bit
  • Linux:
    • Redhat 4, 5, 6 32-bit & 64-bit
    • 64-bit; SUSE 10.1 32-bit

Language Support

  • Verilog 95 and 2001 IEEE-1364 Std
  • VHDL 87 and 93 IEEE 1076 Std
    • std.numeric_bit
    • std.numeric_std
    • ieee.std_logic_1164
    • ieee.std_logic_arith
    • ieee.std_logc_signed
    • ieee.std_logic_unsigned
    • ieee.math_real
  • Mixed-HDL support

Synthesis and Optimizations

  • Optimizations for:
    • Area
    • Speed
    • Balanced
  • Timing driven synthesis optimization
    • Embedded static timing analysis

Devices Supported

  • Lattice MachXO3L device family (Lattice Diamond software)
  • Lattice MachXO2 device family (Lattice Diamond software)
  • Lattice MachXO device family (Lattice Diamond software)
  • Lattice iCE40 device family (Lattice iCEcube2 software)

User Interface

  • Fully integrated in Lattice Diamond® and iCEcube2 design software
  • Tcl extensions for scripting

SDC Supported Constraints

  • create_clock: clock definition
  • create_clock –name name –period <value> [clock port|net]
  • set_input_delay: input setup time requirement
  • set_input_delay <value> -clock [clock port|net] [portlist]
  • set_output_delay: clock to output requirement
  • set_output_delay <value> -clock [clock port|net] [portlist]
  • set_max_delay: max delay requirement for a path
  • set_max_delay <value> -from [port|cell] -to [port|cell]
  • set_multicycle_path: multicycle path definition
  • set_multicycle_path <value> -from [net|cell] –to [net|cell]
  • set_false_path: false path definition
  • set_false_path -from [port|cell] -to [port|cell]
  • Set_false_path –through [net]

HDL Supported Attributes and Directives

  • synthesis: a text macro used with Verilog ‘ifdef directive
  • translate_off/translate_on: instruct LSE to ignore codes between these 2 directives
  • black_box_pad_pin: specify PIOs of a black box
  • syn_black_box: instruct LSE to treat a module/component as a black box
  • syn_keep: instruct LSE to preserve the specified net without optimizing it away
  • syn_noprune: prevents instance optimization for black boxes with unused output ports
  • syn_preserve: prevents sequential optimization such as FSM extraction, etc.
  • loc: specify pin location
  • syn_encoding: VHDL enumerated data type encoding style; support 1-hot, gray and binary
  • syn_hier: control the amount of hierarchical transformation
  • syn_maxfan: control fanout of a port net or registered output
  • syn_ramstyle: specify RAM implementation style; support registers, distributed RAM, block RAM
  • syn_romstyle: specify ROM implementation style; support distributed ROM and EBR
  • syn_useioff: specify whether use I/O registers
  • syn_use_carry_chain: specify whether use carry chain for adders

    (For more details, please check out Online Help.)

Optimization Options

  • Carry Chain Length
    • Maximum # of output bits mapped to a single carry chain
  • EBR Utilization
    • Target percentage of EBR utilization
  • FSM Encoding Style
    • Support 1-hot, Gray and Binary
  • Force GSR
    • Use global set/reset resources
  • MUX Style
    • Support L6Mux Multiple, L6Mux Single and PFU Mux
  • Max Fanout Limit
    • Maximum number of fanouts limiting to the value.
  • Propagate Constants
    • Allow LSE to propagate constant wherever possible to reduce area
  • RAM Style
    • Support embedded block RAM, distributed and registers
  • ROM Style
    • Support EBR or logic
  • Remove Duplicated Registers
    • Eliminate the duplicate Flops
  • Resource Sharing
    • Option to turn of resource restructuring around arithmetic operators.
  • Use Carry Chain
    • Controls the usage of dedicated carry chains for arithmetic operators.
  • Use IO Insertion
    • Enable/Disable IO insertion
  • Use IO Registers
    • User control to pack registers in IO pads
  • Optimization Goal
    • Area, Timing or Balanced
  • Target Frequency (MHz)
    • Only for Timing mode
  • Number of Critical Paths
    • # of critical paths to be reported
  • Hardware Evaluation
    • Enable/disable IP evaluation capability
  • Macro Search Path
    • Paths to physical macro files
  • Memory Initial Value File Search Path
    • Paths to memory initialization file
  • Remove LOC Properties
    • Removes LOC properties in synthesized design
  • Resolved mixed drivers
    • Resolve mixed VCC & GND drivers
  • Output Preference File
    • Carry LDC constraints to LPF

LSE Usage Guidelines for Lattice Diamond

  1. In general, using Area mode is always a good start point
    • Suitable for most designs
    • Default strategy settings are sufficient
    • Timing constraints are unnecessary (ignored)
    • If Fmax reported by PAR TRACE doesn't meet requirement, try the next mode
  2. Use Balance mode, this usually yields better Fmax than Area mode with increased area (LUT)
    • Timing constraints are unnecessary
    • Default strategy settings are sufficient
  3. Use Timing mode if the other two modes do not produce desired results
    • Designer needs to supply appropriate clock and other timing constraints
    • Yields smaller design (LUT) with correct constraints than if not constrained or over constrained
    • Over constraining is unnecessary and not recommended

Lattice Diamond 3.2

  • Adds support for all ECP5 devices
  • Clarity Designer is a new tool with improved design entry methods to allow creating, connecting, and placing systems (ECP5 support only)
  • Reveal support for ECP5 SERDES debug for hardware debugging assistance
  • Adds support for all MachXO3L devices
  • GDDR x4 support in MachXO3L for implementation of high speed interfaces while running core frequency at slower rate such as MIPI D-PHY and subLVDS.
  • LatticeMico System support in MachXO3L for embedded design development.
  • Adds support for MachXO2 LCMXO2-2000ZE in WLCSP49 package.
  • Lattice Synthesis Engine (LSE) expanded support for the following family of devices:
    • MachXO3L device
    • ECP5 devices (pure HDL designs only)
  • LSE expanded to support Synopsis Design Constraints (SDC) for commonly used timing constraints. This facilitates timing constraint entry for users who preferred to use SDC based timing constraints.
  • LSE expanded to support various Synplify Pro's synthesis attributes. This allows users to migrate existing Synplify Pro based design to LSE with minimal rewriting of attributes.
  • Enhanced the Auto Hold Correction algorithm. With the new algorithm, designs with zero setup timing score are more likely to have their hold violations fixed. Furthermore after hold correction, the setup timing score should remain at zero. This feature helps user by increasing the yield of usable designs.
  • Enhanced handling of HDL attributes and edits in Spreadsheet View. The enhancement follows the rule that constraints entered in LPF override those entered in HDL flow.
  • If Synopsys Design Constraints (SDC) are used for synthesis, they can now be automatically translated to LPF language and used in the MAP/PAR process. The LPF file created to accomplish this is not visible from Diamond but the constraints can be seen from SpreadSheet View (SSV) much like HDL attributes can be seen from SSV. Automatically using SDC in MAP/PAR is the default behavior in new projects, but not in existing projects. This feature is enabled/disabled through the synthesis strategy setting: “Use LPF Created from SDC in Project” (both LSE and Synplify). This feature provides a single entry point for timing constraints and can help manage preferences that must be defined on nets.
  • ECO editor log information persists. This allows users to the the log information after closing and reopening the window.
  • Messaging System Enhancements
  • Diamond Programmer Enhancements
  • Deployment Tool Enhancements
  • Programming File Utility Enhancements
  • Model 300 Utility Enhancements
  • Platform Designer Enhancements
    • Updates to VMON table, IMON table, VID IP, and I2C slave address
    • Additional Hot swap support
  • Synopsys Synplify Pro has been updated to version I-2013.09L-SP1-1
  • Aldec Active-HDL LE II has been updated to version 9.3

Lattice Diamond 3.1

  • New device support for select MachXO3 devices (LCMXO3L-2100C caBGA256, LCMXO3L-4300C caBGA256, and LCMXO3L-6900C caBGA256).
  • Lattice Synthesis Engine (LSE) now supports MachXO3 devices.
  • Cloning an existing Diamond Project is now possible by using “Save As…” command. So users can copy a Diamond Project to a different name.
  • Power Calculator has been enhanced with more accurate estimation of the clock network’s power consumption.
  • Programmer now includes full support for iCE40LM devices.
  • Programmer now has Configuration Options Settings. So users can select different device configuration options without having to regenerate a data file.
  • The Programming File Utility now has a Feature Row Editor. This editor provides visual information of the data file’s fuse settings so that users can easily edit the data file to enable or disable silicon features in MachXO2 devices.
  • Reveal Analyzer now supports sample clocks as slow as the JTAG clock speed. This lower frequency increases the range of the sampling clock to a lower minimum from a minimum of 3X of JTAG clock speed.
  • USB driver for Windows OS has been certified by Microsoft. 
  • With the user’s permission, Diamond can now collect and send to Lattice via the internet (only) the WARNING and ERROR messages encountered by the user. This information enables Lattice to improve the users experience.
  • Platform Designer has a “Buffer XO2 outputs for ASC synchronization” option, which adds one register delay from LogiBuilder output to MachXO2 devices’ pins. This option allows users to choose whether ASC and XO2 output signals appear at the same cycle.
  • Platform Designer now includes a User Configurable Hot Swap feature for Platform Manager 2 and ASC devices.
  • Synopsys Synplify Pro has been updated to version I-2013.09L
  • Aldec Active-HDL LE II has been updated to version 9.3

Lattice Diamond 3.0

  • New device support for Platform Manager 2 and companion ASC devices.
  • New message system outputs messages from the implementation engines into the Report View. These messages can now be filtered and sorted to allow users to manage and understand messages better.
  • Platform Designer is a new tool that provides the ability to create and control a complete hardware system using Platform Manager 2 or MachXO2 devices.
  • New option in the file list to allow implementations to be cloned within a project.
  • System Verilog files are now supported in the file list and can be used for implementation. System Verilog files are not supported in LSE, Hierarchy View, HDL Diagram, Simulation Wizard, or Reveal Debugger.
  • Programming File Utility is a new standalone tool that allows programming files to be view and compared.
  • Model 300 Programmer is a new standalone tool that supports the Lattice Model 300 Programmer hardware.
  • Reveal Debugger now supports monitoring power-on reset (POR) functions which happen immediately after powe-on of the hardware.
  • Report View now includes a Tcl commands log in addition to the new messaging system functionality.
  • Spreadsheet View now displays the rows of ports and pins in categorized groups.
  • Run Manager now shows additional information on worst-case slack and timing scores.
  • Synopsys Synplify Pro has been updated to version H-2013.03L
  • Aldec Active-HDL LE II has been updated to version 9.2sp1.

Lattice Diamond 2.2

  • Adds support for MachXO2-4000HE with csBGA184 package.
  • Adds support for LatticeECP3-17 and LatticeECP3-35 automotive grade (LAE3) devices.
  • Online help has updated content for schematic entry.
  • Deployment Tools now supports generating warm boot and cold boot hex files for iCE40 devices when used in standalone mode.
  • IPexpress includes updates for Adder Tree, FFT_Butterfly, Multiply_Add_Sub, and Sin-Cos_Table modules.
  • Strategies now include a new option for VHDL 2008 support in Synplify Pro.
  • LatticeMico System includes a new preprocessor option for LatticeMico EFB for MachXO2 for optimizing code size.
  • Lattice Synthesis Engine (LSE) synthesis tool has been updated.
  • Synopsys® Synplify Pro® for Lattice synthesis tool has been updated with version G-2012.09L-SP1.
  • Active-HDL Lattice Edition II from Aldec was updated to version 9.2sp1.

Lattice Diamond 2.1

  • Lattice Diamond 2.1 is now available as a Linux 64-bit application for RHEL 4, 5, and 6.
  • TRACE and Timing Analysis view now group unconstrained paths by type.
  • TRACE and Timing Analysis view report path details on paths covered by BLOCK preferences.
  • Download Debugger is a new stand-alone software tool for debugging Serial Vector Format (SVF) files, Standard Test And Programming Language (STAPL) files, and Lattice Embedded (VME) files. Debugger allows you to program a device, and edit, debug, and trace the process of SVF, STAPL, and VME files.
  • Lattice Diamond tutorial has been updated with additional content and now supports the ECP3 Versa Development Board
  • The online FPGA Design Guide has a new chapter, HDL Coding Guidelines, which provides VHDL and Verilog design guidelines to help you achieve the best results.
  • The Hierarchy view opens automatically when you open a project. This allows the hierarchy of the design to automatically be shown, preventing confusion on how to show this information.
  • IPexpress shows compatiblity of IP modules with the version of Diamond that you are running by displaying different icons for supported, unsupported, and incompatible versions.
  • LatticeMico™ System include updates to many of it's components including LatticeMico32 microprocessor, and LatticeMico8 microcontroller. See the included documentation for complete details. Additionally LatticeMico™ System allows the generation of platform without a processor and has a new option to significantly improve download speeds of application images.
  • The Place And Route (PAR) report now includes a worst slack value for each place-and-route run. This is the worst timing slack for all timing constraints. Negative values indicate timing violations. You can use this value instead of the timing score to judge the overall timing quality of a run.
  • Multi-seed PAR runs (multi-PAR) now automatically terminate individual runs that do not show improved results over already completed runs. This will normally result in a significant speedup of the total runtime.
  • Diamond Programmer has been updated with several new features:
    • Support has been added for non-Lattice JTAG-ISC and JTAG-STAPL devices.
    • A Custom Device Database has been added, allowing you to add non-Lattice JTAG devices to the device database. This allows Programmer to scan these devices.
    • A Cable Signal Test feature has been added to allow debugging JTAG connections.
    • The Slave SPI Embedded was updated to support SPI Flash programming through the FPGA.
  • Power Calculator has added several new features
    • Power Matrix page shows the amount of power pulled by each component in the design from multiple power sources.
    • Implementation Comparison table compares power consumption among multiple implementations of a design.
    • Average power and thermal comparison table for low-power devices shows an estimate of average power used over time for standby, full power, and shutdown modes.
    • Comparison chart of power awareness for low-power devices compares the amount of power used in standby mode and non-standby mode.
  • Reveal Inserter now parses mixed Verilog and VHDL designs and displays the signal names at the RTL level instead of the netlist (EDIF) level.
  • Simulation Wizard has been improved to allow you to automatically add top level signals to the waveform and then run the simulation.
  • Bitstream file generation for MachXO2 is now supported in addition to JEDEC file generation within the process view.
  • Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, with version G-2012.09L.
  • Active-HDL Lattice Edition II from Aldec was updated to version 9.2.

Lattice Diamond 2.0.1

  • Lattice Diamond 2.0.1 removes the support for LatticeECP4 devices.
  • Diamond Programmer 2.0.1 can be used to configure and program Lattice iCE40 devices. All current iCE40 products/packages are supported for all programming modes (NVCM, SRAM Configuration and External FLASH Programming).
  • Now suport for the ispLEVER Classic and iCE devices has been added to the Aldec® Active-HDL™ Lattice Edition libraries in Diamond. So, if you need to simulate multiple designs targeted to devices available in different software products (e.g. XO, 4KZE, and iCE), please use the Active-HDL version provided with Diamond 2.0.1.
  • With this update, Lattice Diamond has improved timing simulation support for a LatticeECP3 design that includes DDR2 or DDR3 memory interfaces.
  • Improvements to the Schematic Editor have been added, in particular improving zooming of a multi-page schematic and helping with the selection of library components.

Lattice Diamond 2.0

  • Trace Report now includes an improved, unconstrained paths section so users can more quickly identify and fill gaps in their design constraints.
  • With Diamond Programmer 2.0, users can add their own SPI Flash devices directly in the release allowing faster support for these devices.
  • Lattice Diamond Deployment Tool 2.0 also offers improved functionality including file conversion, external memory file generation, improved I2C embedded for the MachXO2 devices and Slave SPI for the LatticeECP3 and LatticeXP2 devices.
  • Stand-alone Power Estimator is now available for power estimation of all devices (including LatticeECP3). It doesn’t require a Diamond Installation; however it requires a free Lattice Diamond license.
  • The FPGA design guide has been revised. Two sections are provided and linked on the start page of the software: Timing Closure and Design Planning.
  • To provide consistent tool behavior from release to release, strategies now include and save all values, not just non-default values, since the default can change from release to release. In a similar fashion, default preferences are saved explicitly when exporting all Spreadsheet Preferences to LPF. This new method can help avoid some of unexpected changes found when upgrading to a new release.
  • The default Router is now Negotiation-Based Router (NBR). It provides about 20 to 30% runtme improvement over CDR, however it requires more CPU memory.
  • A new, partition-based incremental design flow for LatticeECP3™ and LatticeECP2/M FPGA devices will help preserve design performance and reduce run time after a design change is made.
  • In addition to the 32-bit application for Windows XP and Vista, Lattice Diamond 2.0 software is now also provided as a 64-bit application for Windows 7 to increase memory capacity to support larger devices. For Linux users, Lattice Diamond 2.0 now runs on Linux Red Hat 6 in addition to versions 5 and 4.
  • Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, with version F-2012.03L.
  • Active-HDL Lattice Edition II from Aldec was updated to version 9.1.

Lattice Diamond 1.4.2

  • Lattice Diamond 1.4.2 is an update to Lattice Diamond 1.4. Before installing this update, please install version 1.4 of Lattice Diamond.
  • Lattice Diamond 1.4.2 addresses an issue found in Lattice Diamond 1.4, where a design targeted to a LatticeECP3 Low Power FPGA (-6L, -7L or -8L) may not show the same timing performance as the regular LatticeECP3 FPGA (the non -L or-6, -7,-8) as expected.
  • With this update, support is added for the new 32QFN package of the 256 MachXO2 device and support for MachXO2 WLCSP-49 device has been removed.
  • The IPexpress tool EFB module graphical user interface (GUI) now has Wishbone checkbox that allows the user to provide access to embedded flash memories in all MachXO2 devices, without instantiating un-needed interfaces like I2C and SPI
  • For MachXO2, the UFM/Configuration I2C slave address is clearly displayed in the IPexpress EFB module I2C Configuration tab and in the Map report.
  • For MachXO2, the keyword MUX_CONFIGURATION_PORTS has been added to the sysCONFIG preference. This feature allows all Configuration ports to be disabled in order to provide additional user I/Os. It can be set to ENABLE or DISABLE in Diamond’s Spreadsheet View or manually in the logical preference file.
  • The Soft Error Detect (SED) during normal active operation has been removed from LatticeXP2 and LatticeECP2/M devices. Refer to PCN 02B-12 Notification of a Revision to the LatticeXP2, LA-LatticeXP2 and LatticeECP2/M Data Sheets. The SED function can still run on a programmed device when the user logic is inactive. 

Lattice Diamond 1.4

  • Lattice Diamond 1.4 software provides final timing and power analysis device information, as well as final production package, bit stream data based on the actual silicon characterization for all the MachXO2 devices.
    • The final simultaneous switching output (SSO) data is available for all packages except for the wafer-level chip scale package of the LCMXO2-2000U that will be provided later
    • The quality of results (QoR) is at par with what was obtained with version 1.3 on most designs targeted to the LCMXO2 devices
  • To get timing closure faster, users can now use a new PAR strategy setting “Stop Once Timing is Met” to get multi-PAR to stop after either trying a maximum number of seeds or when the last seed run has resulted in a timing score of zero – whichever comes first.
  • LSE users can now create and edit Synopsys Design Compiler (SDC) synthesis constraints in the new Lattice Design Constraints graphical editor. This editor automatically populates design clock, port and net names and provides real time syntax and semantic checks. It generates an SDC file that can be used with LSE.
  • With this release comes the new Diamond Deployment Tool. It uses an intuitive wizard approach to create the appropriate device programming file in the format required by the user’s deployment method. Diamond Deployment Tool is a standalone tool available as an accessory in the Lattice Diamond environment.
  • With Lattice Diamond 1.4, users can pause, stop and resume per seed, any of the multi-PAR jobs run under Run Manager. They can export the results in a CSV file, and they can also compare run reports of multiple implementations side by side and easily determine the best implementation for their design.
  • Using Run Manager, users can individually control the maximum number of implementations and multi-PAR processes that can be run simultaneously. Parallel processing is only supported on a single computer with a multi-core CPU. Parallel processing across multiple computers is not currently supported.
  • Lattice Diamond will help users migrate their designs to a lower cost device within the same device family while preserving the current package and board layout. This capability has now been extended to all the Lattice device families supported by Lattice Diamond software. Users are provided pin migration information in the Package view and Spreadsheet views, such as incompatible pins. This pin migration information can also be exported to the Pin Layout file.
  • Lattice Diamond 1.4 software now displays in the hierarchy view resources used by each level of design hierarchy following either the synthesis or the map step. Device resources can therefore be displayed as both logical (registers) and physical (slices) elements. This feature helps users quickly understand what parts of their design are using scarce device resources so that they can optimize the design for the targeted device. This information can now also be exported to a text or a CSV file to enable analysis in other tools.
  • With this release, the pin assignment Design Rule Check (DRC) engine has been redesigned and implemented for the LatticeECP3™, MachXO2 and LatticeSC™ device families to provide real-time as well as on-demand DRC during pin assignment and configuration, and a user-friendly report helps identify and correct pin usage issues.
  • Users can now insert an unlimited number of custom columns in Port and/or Pin Assignments tabs of Spreadsheet View. User can use these columns to comment/document per port or pin. The order of the column can be changed via drag and drop. The information can be exported to or imported from a Pin Layout File. It will not be included in LPF files and will not affect the processing.
  • With this release of Reveal, Token Manager was moved from Reveal Inserter to Reveal Analyzer. This allows tokens to be changed without re-inserting debug and resetting the process list. However it doesn’t allow tokens to be defined before running Analyzer.
  • Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, with version F-2011.09L, released in September 2011.
  • Active-HDL Lattice Edition II from Aldec was updated to version 8.3SP1.

Lattice Diamond 1.3.1

  • Lattice Diamond 1.3.1 is an update to Lattice Diamond 1.3. Before installing this update, please install version 1.3 of Lattice Diamond.
  • Lattice Diamond 1.3.1 adds support to the 328 csBGA 10x10mm, 0.5 mm pitch wire bonded package for the LatticeECP3 17K devices with both industrial and commercial grading.
  • There are improvements made to Reveal in Diamond 1.3.1 to address three issues:
    • In some cases with Lattice Diamond 1.3, the waveform output is not correct when using 3 TUs and having a Max Sequence Depth of Trigger Expression (TE) set to 4.
    • In some cases, when using LatticeECP3 distributed DP RAM, Reveal would fail with a “circuit has too large data_width” error message.
    • The Inserter GUI sometimes reports "Catch unknown exception".

Lattice Diamond 1.3

  • Lattice Diamond 1.3 software provides updated timing and power analysis device information, as well as final production package, bit stream and SSO analysis data based on the actual silicon characterization for the MachXO2 LCMXO2-1200 and LCMXO2-1200U devices.
  • These changes, plus ongoing improvements to the synthesis, MAP and PAR implementation engines, have resulted in an FMax improvement of 5% to 15% on most designs targeted to the LCMXO2 devices.
  • Lattice Diamond 1.3 adds support for a wafer-level package for the LCMXO2-2000U that is needed for very high volume, cost sensitive applications.
  • Lattice Diamond 1.3 software provides device resource utilization for each logical level of the design hierarchy following synthesis, and enables users to make early design decisions about how to structure their design so that they can optimize utilization of the overall device.
  • Designers can add user-defined clock jitter to their design’s clocks while they are performing static timing analysis of these designs. Users control the amount of clock jitter through an extension to the existing Trace timing preferences, and see the analysis results in both the Trace report and the Timing Analysis View.
  • Software provides features to help migrate a design to a lower cost device while preserving the current package and board layout. This capability is available for MachXO2 and LatticeECP3 devices. Users get incompatible pin information in the Package View and Spreadsheet View. This pin migration information can also be exported to the Pin Layout file.
  • Projects can now support complex multi-file test benches and allow multiple design representations for the same design block (such as for synthesis and a different one for simulation).
  • The simulation wizard can automatically determine which files should be set to simulation and pass the correct options to the simulator.
  • The synthesis design constraints flow allows for multiple files (SDC and/or LDC files) that can be managed similar to the back-end preference files (LPF files).
  • Using Reveal Analyzer, users can now download large trace data amounts and configure complex trigger setups more than 10 times faster than previously possible.
  • With Diamond Programmer, users can program the devices from within Diamond in a much easier way than ispVM for the most common steps such as setting up the cable, scanning the board, and direct programming of the device.
  • Users can directly select the active implementation in Run Manager and also control which one of the multi-par runs is used so that the rest of the design flow can be focused on the implementation that provides the best placement and routing run for that design.
  • Lattice Diamond 1.3 supports the Platform Manager devices
  • Users can manage, document and export the information about the package pin out for early pin planning and pin assignment exchange with PCB designers and/or third party tools for pin assignment signoff and design document. Users can get a device's package pin information right from within Diamond

Lattice Diamond 1.2

  • MachXO2 users can now generate complete systems based on the LatticeMico8™ open-source 8-bit controller core using version 1.2 of the open-source Eclipse based LatticeMico™ System.
  • Lattice Diamond 1.2 adds the support for all the ultra-high I/O count MachXO2™ devices, and the wafer level packages needed for very high volume cost sensitive applications.
  • Lattice Diamond 1.2 software now includes updated power, timing and SSO analysis values based on the actual silicon characterization for the LCMXO2-1200 and LCMXO2-1200U devices of the MachXO2 PLD family.
  • Reveal hardware debugger has been validated with the actual silicon of these MachXO2 devices.
  • With Lattice Diamond 1.2 release, users can now tailor the flow to auto-create the reports they want to read after each process sub-step.
  • Power Calculator has been enhanced so it generates the Activity Factor from the VCD file and handles internal signals, not just top-level ports. The VCD file needs to be gate level and matching with the design.
  • ECO Editor now supports User Flash Memory (UFM) initialization for MachXO2-640 and higher density devices.
  • The EBR and distributed memory initialization feature was also enhanced to include the Update Initial Memory dialog box for specifying the initialization settings.
  • To simplify the user interface and avoid confusion, I/O SSO (simultaneous switching output) Analysis was removed from the Place & Route stage of the Process view, however is still available through Spreadsheet View and Package View.
  • Logic Block View  now opens as a separate view with its own vertical toolbar. One or more Logic Block Views can be opened from components in Floorplan View, Physical View, or NCD View.
  • Predefined Layouts Four predefined layouts are now available from the Window menu for common design tasks: Analyze RTL, Enter Preferences, Manage Project, and Timing Analysis.
  • Reports View now includes “Generate Hierarchy” and “Run BKM Check” reports. These reports make this information easier to find and provide more detail. Previously this information was only available in the Output view.
  • IPexpress™ contains numerous improvements to existing modules.
  • ispVM® System software has been upgraded to version 18.0.
  • Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, with version E-2010.09-SP2, released in December 2010.
  • Lattice Diamond 1.2 release supports Tcl 8.5.

Lattice Diamond 1.1

  • Initial support for MachXO2 device family.
  • Introduction of Lattice Synthesis Engine (LSE) supporting MachXO2 and MachXO devices families. LSE is the result of several years of development initially focused on Lattice's internal FPGA architecture development. LSE supports both Verilog and VHDL languages and uses SDC format for constraints. It is integrated into the Lattice Diamond design software as a synthesis tool choice when a supported device family is selected.
  • Performance improvements on large designs resulting in up to 20% faster FMax results.
  • LatticeECP3 family final data is included in this software release for timing, power, and SSO noise.
  • Strategy options  have been added for LSE support and Update Compile Point Timing.
  • Floorplan View includes a new “Display Congestion” command that has been added which shows a representation of the amount of routing congestion for a PLC component or site.
  • Power Calculator includes new features that have been added for the MachXO2 low power architecture, including Power Option Controller and an EFB page for the embedded function block.
  • Spreadsheet View Spreadsheet View includes enhancements for the BLOCK preference.
  • Source Editor now provides SDC templates for use with VHDL and Verilog HDL files editing.
  • Timing Analysis View has significant performance improvements for recalculating both path delays and changing default speed grade settings.
  • IPexpress™ contains numerous improvements to existing modules and also includes new modules specifically for MachXO2.
  • ispVM® System software has been upgraded to version 17.9.
  • Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, including improved targeting of behavioral HDL to ECP3 sysDSP block cascade feature resulting in higher performance filters.
  • Aldec® Active-HDL™ Lattice Edition simulator has been updated.

Lattice Diamond 1.0

New software introduction. New feature introductions in the following areas greatly increase the software functionality and ease of use over previous software design environments.

  • Design Exploration
    • Design projects in Diamond offer an order of magnitude increased functionality by allowing more robust projects and capabilities that allow design exploration. Key improvements to Diamond projects include the following.
      • Allow the mixing of Verilog, VHDL, EDIF, and schematic sources
      • Implementations, allow multiple versions of a design within a single project
      • Strategies allow implementation “recipes” to be applied to any implementation within a project or shared between projects
      • Manage and choose files for constraints, timing analysis, power calculation, and hardware debug
    • Use Run Manager view to allow parallel processing of multiple implementations in order to explore design alternatives for the best results.
    • Save time by analyzing your design prior to synthesis with the new integrated HDL code checking capability.
  • Ease of Use Throughout
    • The Diamond user interface combines leading edge features and customization while offering better ease of use. All the tools in Diamond now open in “Views” integrated into a common Diamond user interface and have the ability to be detached in separate windows. Once the operation for a single tool view is learned, this knowledge can be applied to other views. New features like the Start Page and Reports view allow easy access to information.
    • ECO Editor provides quick access to commonly used netlist editing functions such as sysIO settings, PLL parameters, and memory initialization. Programmer allows fast reprogramming of FPGAs once the hardware configuration has been setup with ispVM. Getting the job done more quickly is the goal of these tools
  • More Efficient Design Flow
    • The new Timing Analysis view offers an easy to use graphical environment for navigating timing information. A key new benefit in Timing Analysis view is rapidly updated analysis when timing constraints are changed. No longer must you re-implement your design to re-run a TRACE report.
    • Diamond provides easy export of designs to simulators through the new Simulation Wizard.
    • Diamond software adds new capabilities for scripting the design flow. Diamond specific TCL command dictionaries are available for projects, netlists, HDL code checking, power calculation, and hardware debug insertion and analysis. 

Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. The videos below include an overview of new features in Diamond along with several key improvements and changes in specific areas from earlier software environments. Click on the video links to download an MP4 file which you can then play in your video player of choice.


Available Videos
Video Title Time Size Abstract
Diamond Overview 14:48 28MB Lattice Diamond software includes many new features. This video overview briefly covers several new features and abilities such as the new user interface, design flow, and several tool views that are available.
Diamond Key Concepts 10:25 21MB Lattice Diamond software includes several new key concepts. This video discusses the structure of Diamond projects and the use of implementations, strategies, and folders within projects. Additionally the video discusses shared design memory use, and context sensitive views.
Diamond Importing from ispLEVER 4:47 10MB Lattice Diamond software uses a different project structure than the previous ispLEVER software. This video describes how to import an ispLEVER project into Diamond.
Diamond Design Flow Changes 8:23 16MB Lattice Diamond software features a similar design flow to previous software with some changes and enhancements. This video describes the design process flow and the use of the Process view, File List view, and Run Manager view.
Diamond Timing Analysis Overview 9:36 21MB Lattice Diamond software includes a new Timing Analyzer View that provides a rich graphical interface to viewing timing constraint paths, reports, and schematics. Additionally, the ability to change timing constraints and directly run a timing analysis without re-implementing the design significantly speeds the timing closure process. This video describes the management of the Timing Analyzer files, the new Timing Analyzer UI, and how to make timing constraint changes and generate new timing results.
Diamond Power Calculator 5:06 13MB Lattice Diamond software includes an improved Power Calculator view. A new feature is the ability to manage power project files (PCF) directly in the File List view. This video describes the management of the Power Calculator files and the behavior of the Power Calculator view.
Diamond Reveal Hardware Debugger 8:09 14MB Lattice Diamond software includes improved Reveal Inserter and Reveal Analyzer views for hardware debugging. The Reveal Analyzer view features a streamlined interface including an updated waveform display featuring multiple cursors and rubber banding for measurements. This video describes the management of the Reveal debug files and the new Reveal Analyzer waveform changes.
Diamond Simulation Flow 6:37 11MB Lattice Diamond software includes changes to projects that support multi-file simulation testbenches and allow different models for simulation or synthesis for a single module. The Simulation Wizard has been enhanced to parse for the simulation top and to pass this information and other options directly to a simulator. This video describes the simulation features provided with the software and their basic usage.
Diamond Tcl Scripting Support 2:41 5MB Lattice Diamond software includes new Tcl dictionaries that provide the ability to script the design flow and several key views. This video describes the available Tcl dictionaries and how to run Tcl commands from the UI or the Tcl console.
Diamond Programmer 4:17 6MB Lattice Diamond software includes Programmer that provides the ability to directly program one or multiple FPGA devices on the same scan chain. This video describes how to use it from the UI or outside of DIamond.

Lattice Diamond Software Free License

To request a license you will need the following:

  • Lattice website user account
  • Physical MAC address (12-digit hexadecimal value)

Click here to request your license.

Diamond Versa Kit Free License

To request a license you will need the following:

  • Lattice website user account
  • Physical MAC address (12-digit hexadecimal value)

Click here to request your license.

Lattice Diamond Subscription License

To request a license you will need the following:

  • Lattice website user account
  • Physical MAC address (12-digit hexadecimal value)
  • Aldec USB Key serial number (only for floating licenses)
  • Lattice Diamond serial number

Click here to request your license.

Lattice Diamond Subscription License 5-Day Extension

This license is only for a temporary extension to a subscription license that has expired.

To request a license you will need the following:

  • Lattice website user account
  • Lattice Diamond serial number

Click here to request your temporary 5-day license.

Lattice Diamond Software Application Note

  TITLE NUMBER VERSION DATE FORMAT SIZE
Jitter Analysis in Lattice Diamond TN1241 1.1 9/20/2011 PDF 1.4 MB
LatticeMico32 Migration Concerns Post ispLEVER 8.1 and Diamond 1.0 TN1221 11/5/2010 PDF 404.1 KB
Using Lattice Diamond Pin Layout Files and Pinout Files AN8087 1.0 7/18/2011 PDF 160.2 KB

Lattice Diamond Software Data Sheet

  TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeMico Embedded Function Block 3.2 6/27/2014 PDF 417.6 KB
LatticeMico Fault Logger 3.1 2/26/2014 PDF 177.6 KB
LatticeMico GPIO 3.1 2/19/2014 PDF 312.9 KB
LatticeMico SDRAM 3.1 2/26/2014 PDF 964.8 KB
LatticeMico SPI Flash 3.1 2/26/2014 PDF 243.9 KB
LatticeMico VID 3.2 3.2 6/27/2014 PDF 203.2 KB

Lattice Diamond Software Installation Guides

  TITLE NUMBER VERSION DATE FORMAT SIZE
Diamond 3.2 Installation Guide for Linux 3.2 6/27/2014 PDF 459.9 KB
Diamond 3.2 Installation Guide for Windows 3.2 6/27/2014 PDF 702.8 KB

Lattice Diamond Software Known Issues

  TITLE NUMBER VERSION DATE FORMAT SIZE
Diamond 3.2 Known Issues 3.2 6/27/2014 PDF 462.9 KB

Lattice Diamond Software Product Brochure

  TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice Diamond Software Product Brief I0207 3.0 1/8/2014 PDF 2.2 MB
Lattice Diamond Software Product Brief (Chinese Language Version) I0207C 3.0 1/8/2014 PDF 1.4 MB

Lattice Diamond Software Product Change Notification

  TITLE NUMBER VERSION DATE FORMAT SIZE
PCN10A-11 Notification of Intent to Freeze ispLEVER After Version 8.2 PCN10A-11 1.0 7/25/2011 PDF 52.7 KB

Lattice Diamond Software Release Notes

  TITLE NUMBER VERSION DATE FORMAT SIZE
Diamond 3.2 Release Notes 3.2 6/27/2014 PDF 154 KB
LatticeMico System for Diamond 3.2 Release Notes 3.2 6/27/2014 PDF 120.8 KB
Software Cable Support 2.0 7/16/2012 PDF 194.8 KB

Lattice Diamond Software Tutorials

  TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice Diamond Tutorial 3.2 6/27/2014 PDF 2.3 MB
Lattice Synthesis Engine Tutorial 3.1 3.1 2/26/2014 PDF 244.3 KB
LatticeMico32 Tutorial for Diamond 3.2 6/27/2014 PDF 8.1 MB
LatticeMico8 Tutorial 3.1 2/26/2014 PDF 5.5 MB

Lattice Diamond Software User Manual

  TITLE NUMBER VERSION DATE FORMAT SIZE
Clarity User Guide 3.2 3.2 6/27/2014 PDF 514 KB
Design Planning 3.1 2/26/2014 PDF 1.8 MB
Diamond 3.2 User Guide 3.2 6/27/2014 PDF 4 MB
FPGA Libraries Reference Guide 3.2 3.2 6/27/2014 PDF 2.2 MB
HDL Coding Guidelines 2.1 2/21/2013 PDF 209.2 KB
LatticeMico32 HW User Guide 3.2 6/27/2014 PDF 1.4 MB
LatticeMico32 SW Developer User Guide 3.2 6/27/2014 PDF 5 MB
LatticeMico8 Developer User Guide 3.2 6/27/2014 PDF 3.2 MB
PAC-Designer Software User Manual 6.28 6.28 6/27/2014 PDF 3.3 MB
Platform Designer 3.1 User Guide 3.1 2/26/2014 PDF 1.6 MB
Programming Tools User Guide 3.2 3.2 6/27/2014 PDF 4.6 MB
Reveal 3.1 Troubleshooting Guide 3.1 2/26/2014 PDF 138.7 KB
Reveal 3.2 User Guide 3.2 6/27/2014 PDF 672.1 KB
Timing Closure 3.1 2/26/2014 PDF 1.1 MB

Lattice Diamond Software Downloadable Software

  TITLE NUMBER VERSION DATE FORMAT SIZE
Diamond 3.2 32-bit Encryption Pack for Linux 3.2 6/27/2014 724 KB
Diamond 3.2 32-bit Encryption Pack for Windows 3.2 6/27/2014 2.8 MB
Diamond 3.2 32-bit for Linux 3.2 6/27/2014 RPM 1.2 GB
Diamond 3.2 32-bit for Windows 3.2 6/27/2014 ZIP 1.5 GB
Diamond 3.2 64-bit Encryption Pack for Linux 3.2 6/27/2014 723 KB
Diamond 3.2 64-bit Encryption Pack for Windows 3.2 6/27/2014 2.8 MB
Diamond 3.2 64-bit for Linux 3.2 6/27/2014 RPM 1.2 GB
Diamond 3.2 64-bit for Windows 3.2 6/27/2014 ZIP 1.5 GB
LatticeMico System for Diamond 3.2 32-bit Linux 3.2 6/27/2014 RPM 405.1 MB
LatticeMico System for Diamond 3.2 64-bit Linux 3.2 6/27/2014 RPM 350.7 MB
LatticeMico System for Diamond 3.2 Windows 3.2 6/27/2014 ZIP 383 MB
Linux Installers MD5 Checksums 3.2 3.2 6/27/2014 TGZ 0.8 KB
ORCAstra Standalone 3.2 for Windows 3.2 6/27/2014 ZIP 30 MB
PAC Designer 6.28 for Windows 6.28 6/27/2014 ZIP 120.2 MB
Power Estimator 3.2 32-bit for Linux 3.2 6/27/2014 RPM 303.7 MB
Power Estimator 3.2 32-bit for Windows 3.2 6/27/2014 ZIP 225.2 MB
Power Estimator 3.2 64-bit for Linux 3.2 6/27/2014 RPM 238 MB
Power Estimator 3.2 64-bit for Windows 3.2 6/27/2014 ZIP 246.1 MB
Programmer Standalone 3.2 32-bit for Linux 3.2 6/27/2014 RPM 115 MB
Programmer Standalone 3.2 32-bit for Windows 3.2 6/27/2014 ZIP 49.2 MB
Programmer Standalone 3.2 64-bit for Linux 3.2 6/27/2014 RPM 58 MB
Programmer Standalone 3.2 64-bit for Windows 3.2 6/27/2014 ZIP 57.3 MB
Programmer Standalone Encryption Pack 3.2 32-bit for Linux 3.2 6/27/2014 28 KB
Programmer Standalone Encryption Pack 3.2 32-bit for Windows 3.2 6/27/2014 1.9 MB
Programmer Standalone Encryption Pack 3.2 64-bit for Linux 3.2 6/27/2014 28 KB
Programmer Standalone Encryption Pack 3.2 64-bit for Windows 3.2 6/27/2014 1.9 MB
Reveal Standalone 3.2 32-bit for Linux 3.2 6/27/2014 RPM 106.8 MB
Reveal Standalone 3.2 32-bit for Windows 3.2 6/27/2014 ZIP 44.8 MB
Reveal Standalone 3.2 64-bit for Linux 3.2 6/27/2014 RPM 49.9 MB
Reveal Standalone 3.2 64-bit for Windows 3.2 6/27/2014 ZIP 53.2 MB