ECP5 Chip Shot

ECP5 FPGA Family

Low cost, Low power, Small form factor

Cost optimized architecture – Focused on providing low cost connectivity to ASICs and ASSPs with improved routing architecture, dual channel SERDES, and enhanced DSP blocks for up to 4x improved multiplier utilization.

Small packages with high functional density – Up to 85K LUTs in 10 x 10 mm, 0.5 mm pitch package with SERDES. Smart ball depopulation simplifies package integration with existing low cost PCB technology.

Low power consumption – Low static and dynamic power with single channel SERDES functions below 0.25 W and quad channel SERDES functions below 0.5 W.

Testing 4

ECP5 breaks the rule that all FPGAs should be the highest density, power hungry, and expensive. With a focus on compact, high volume applications, Lattice optimized the ECP5 architecture for low cost, small form factor and low power consumption. These characteristics make the ECP5 devices ideal for delivering programmable connectivity solutions to complement ASICs and ASSPs.

Dual channel SERDES

  • 270 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit SERDES, and 8-bit SERDES modes
  • Up to 4 channels per device in dual channel blocks for higher granularity
  • PCI Express, Ethernet (1GbE, SGMII, XAUI), CPRI, SMPTE 3G and JESD204B

Enhanced DSP Blocks

  • Booster logic for double data rate (DDR) mode provides 2x resource improvement
  • Pre-adder support provides 2x resource improvement for symmetrical filters
  • Flexible cascading across DSP slices minimizes fabric utilization for common functions

Programmable I/O

  • DDR2/DDR3 & LPDDR2/LPDDR3 memory support with DQS logic, up to 800 Mbps data-rate
  • LVCMOS 33/25/18/15/12, 7:1 LVDS, XGMII, LVTTL
  • LVDS, Bus-LVDS, LVPECL, MIPI D-PHY input interfaces

Low Power Consumption

  • Low static power typically under 80 mW
  • Low dynamic power with 1.1 V core voltage
  • Standby mode for SERDES and dynamic IO bank controllers

Package Optimizations

  • Low cost flip chip and 0.5 mm/0.8 mm pitch support
  • Smart depopulation to ease PCB routing
  • Up to 85K LUTs in compact 10 x 10 mm package

ECP5 Device Selection Guide

Device LFE5UM-25 LFE5UM-45 LFE5UM-85 LFE5U-25 LFE5U-45 LFE5U-85
LUTs (K) 24 44 84 24 44 84
sysMEM Blocks (18Kbits) 56 108 208 56 108 208
Embedded Memory (Kbits) 1008 1944 3744 1008 1944 3744
Distributed RAM Bits (Kbits) 194 351 669 194 351 669
18x18 Multipliers 28 72 156 28 72 156
SERDES (Dual/Channel) 1/2 2/4 2/4 0 0 0
PLLs/DLLs 2/2 4/4 4/4 2/2 4/4 4/4
Packages and SERDES Channels I/O Combinations
285 csfBGA (10x10 mm, 0.5 mm) 2/118 2/118 2/118 0/118 0/118 0/118
381 caBGA (17x17 mm, 0.8 mm) 2/197 4/203 4/205 0/197 0/203 0/205
554 caBGA (23x23 mm, 0.8 mm) 4/245 4/259 0/245 0/259
756 caBGA (27x27 mm, 0.8 mm) 4/365 0/365

ECP5 FPGAs provide a low cost, low power, small form factor solution for implementing connectivity and video and imaging functionality in high volume applications such as small cells, industrial video cameras and broadband access equipment.

Low Cost Connectivity for Small Cell Wireless Base Stations

  • Flexible interfacing options to digital front end (DFE) including CPRI, ORI and compressed CPRI
  • DFE augment processing for pico cells such as multi-carrier DUC/DDC and CFR
  • Flexible interfacing options to analog front end including LVDS,JESD207, and JESD204B

Low Power Integration for Industrial Video Cameras

  • Direct interfacing capability with single or multiple image sensors (MIPI CSI-2, sub-LVDS, HiSPi, Parallel)
  • High-performance Wide Dynamic Range (WDR) and Image Signal Processing capabilities supported by embedded block RAM (EBR), and embedded DSP blocks
  • Flexible video interfacing options including integrated high-speed SERDES channels, LVDS, PCIe, and GigE

Small Form Factor Solution for Smart SFPs

  • Smart SFP solution with integrated Operation and Maintenance (OAM) for remote control
  • ECP5 in 10 x 10 package enables small form factor solution for optical modules
  • SERDES and triple speed MAC for low cost, low power connectivity

ECP5 PCI Express Development Kit

The PCI Express development kit includes an easy-to-use evaluation board that enables designers to investigate and experiment with the features of the ECP5 FPGA, with specific focus on enabling PCIe technology evaluation with various demos. Click here for more information.

Lattice Diamond Design Software

Leading-edge design software for Lattice FPGA families. A complete design environment tailored for Lattice devices with an easy-to-use interface, superior design exploration, optimized design flow, Tcl scripting and more. Click here request Diamond software for ECP5.

ECP5 FPGA Family Application Note

Advanced Security Encryption Key Programming Guide TN1215 1.3 3/4/2014 PDF 4.6 MB
Dual and Mulitple Boot Feature TN1216 1.5 3/4/2014 PDF 3.9 MB
ECP5 Hardware Checklist TN1269 1.0 3/26/2014 PDF 475.1 KB
ECP5 High-Speed I/O Interface TN1265 1.0 2/26/2014 PDF 7.7 MB
ECP5 Memory Usage Guide TN1264 1.0 2/26/2014 PDF 5.7 MB
ECP5 SERDES/PCS Usage Guide TN1261 1.0 2/26/2014 PDF 8.2 MB
ECP5 sysCLOCK PLL/DLL Design and Usage Guide TN1263 1.0 2/26/2014 PDF 4.6 MB
ECP5 sysCONFIG Usage Guide TN1260 1.2 8/5/2014 PDF 4.1 MB
ECP5 sysDSP Usage Guide TN1267 1.0 2/26/2014 PDF 2.8 MB
ECP5 sysIO Usage Guide TN1262 1.0 2/26/2014 PDF 1.6 MB
PCB Layout Recommendations for BGA Packages TN1074 2.9 6/26/2014 PDF 8.6 MB
Power Consumption and Management for ECP5 Devices TN1266 1.0 2/26/2014 PDF 1.4 MB
Soft Error Detection SED Usage Guide TN1184 1.5 3/3/2014 PDF 1022.5 KB
Sub-LVDS Signaling Using Lattice Devices TN1210 1.2 3/4/2014 PDF 695.3 KB
Using TraceID TN1207 1.6 6/24/2014 PDF 732.5 KB
Using TransFR Technology TN1087 3.5 3/4/2014 PDF 2.4 MB

ECP5 FPGA Family Data Sheet

ECP5 Family Data Sheet DS1044 1.2 8/26/2014 PDF 7.9 MB
ECP5U caBGA381 Migration 1.1 4/10/2014 CSV 30.5 KB
ECP5U caBGA554 Migration 1.1 4/10/2014 CSV 29.4 KB
ECP5U csfBGA285 Migration 1.0 4/10/2014 CSV 21.6 KB
ECP5U-25 Pinout 1.1 4/10/2014 CSV 17.5 KB
ECP5U-45 Pinout 1.1 4/10/2014 CSV 24.2 KB
ECP5U-85 Pinout 1.1 4/10/2014 CSV 35.9 KB
ECP5UM caBGA381 Migration 1.1 4/10/2014 CSV 32 KB
ECP5UM caBGA554 Migration 1.1 4/10/2014 CSV 30.6 KB
ECP5UM csfBGA285 Migration 1.0 4/10/2014 CSV 22.2 KB
ECP5UM-25 Pinout 1.1 4/10/2014 CSV 18 KB
ECP5UM-45 Pinout 1.1 4/10/2014 CSV 25.1 KB
ECP5UM-85 Pinout 1.1 4/10/2014 CSV 36.9 KB
Package Diagrams 4.5 8/14/2014 PDF 13.6 MB

ECP5 FPGA Family Hand Book

ECP5 Family Handbook HB1012 1.0 3/26/2014 PDF 45 MB

ECP5 FPGA Family Product Brochure

ECP5 Product Brochure 1.0 4/1/2014 PDF 837.4 KB

ECP5 FPGA Family Schematic Symbols

Lattice OrCAD Capture Schematic Library (OLB) 4.0 7/16/2014 ZIP 946.6 KB

ECP5 FPGA Family User Manual

ECP5 PCI Express Board User's Guide EB91 1.0 7/31/2014 PDF 4.3 MB

ECP5 FPGA Family Delphi Models

ECP5 Device Family DELPHI Models 1.0 2/21/2014 ZIP 75.6 KB

ECP5 FPGA Family IBIS Model

[IBIS] ECP5 1.0 2/21/2014 IBS 26.6 MB

ECP5 FPGA Family Reference Design

Advanced SDR SDRAM Controller - Design Documentation RD1010 4.7 3/12/2014 PDF 920.7 KB
Advanced SDR SDRAM Controller - Source Code RD1010 4.7 3/12/2014 ZIP 552.4 KB
BSCAN2 - Multiple Boundary Scan Port Linker - Source Code RD1002 4.6 3/13/2014 ZIP 2.6 MB
BSCAN2 - Multiple Scan Port Linker - Documentation RD1002 4.6 3/5/2014 PDF 1.2 MB
HDMI/DVI Video Interface Reference Design RD1097 1.4 3/1/2014 PDF 3.5 MB
HDMI/DVI Video Interface Reference Design - Source Code RD1097 1.4 4/9/2014 ZIP 6.8 MB
HiSPi-to-Parallel Sensor Bridge RD1120 1.3 4/1/2014 PDF 734.9 KB
HiSPi-to-Parallel Sensor Bridge - Source Code RD1120 1.3 4/9/2014 ZIP 342.6 KB
I2C (Inter-Integrated Circuit) Master Controller - Documentation RD1005 5.8 3/6/2014 PDF 987.4 KB
I2C (Inter-Integrated Circuit) Master Controller - Source Code RD1005 5.8 3/18/2014 ZIP 1.1 MB
I2C (Inter-Integrated Circuit) Slave/Peripheral - Documentation RD1054 1.5 3/1/2014 PDF 800.8 KB
I2C (Inter-Integrated Circuit) Slave/Peripheral - Source Code RD1054 1.5 3/12/2014 ZIP 803 KB
I2C Controller for Serial EEPROMs - Documentation RD1006 2.6 3/5/2014 PDF 767.9 KB
I2C Controller for Serial EEPROMs - Source Code RD1006 2.6 3/12/2014 ZIP 751.8 KB
I2C Master with WISHBONE Bus Interface - Documentation RD1046 1.5 3/12/2014 PDF 1.4 MB
I2C Master with WISHBONE Bus Interface - Source Code RD1046 1.4 4/12/2011 ZIP 1.4 MB
RGMII to GMII Bridge - Source Code RD1022 2.2 3/1/2014 ZIP 331.4 KB
RGMII to GMII Bridge Reference Design RD1022 2.2 3/1/2014 PDF 437.1 KB
SD Flash Controller Using SD Bus - Documentation RD1088 1.4 3/12/2014 PDF 1.4 MB
SD Flash Controller Using SD Bus - Source Code RD1088 1.4 3/12/2014 ZIP 5 MB
Sony Parallel sub-LVDS Sensor Bridge - Source Code RD1122 1.6 3/1/2014 ZIP 940.8 KB
Sony Parallel Sub-LVDS-to-Parallel Sensor Bridge User's Guide RD1122 1.6 3/25/2014 PDF 555.9 KB

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