Why pay more for less? – Costing 40% less than competing FPGAs, ECP5 provides connectivity to ASICs and ASSPs with improved routing architecture, dual channel SERDES, and enhanced DSP blocks for up to 4x improved multiplier utilization.
Small packages, twice the functional density – ECP5 provides to 85 K LUTs in 10.0 x 10.0 mm, 0.5 mm pitch package with SERDES. Smart ball depopulation simplifies package integration with existing low cost PCB technology.
30% lower power consumption – Low static and dynamic power with single channel SERDES functions below 0.25 W and quad channel SERDES functions below 0.5 W.
- 270 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit SERDES, and 8-bit SERDES modes
- Up to 4 channels per device in dual channel blocks for higher granularity
- Enhanced DSP blocks provide 2x resource improvement for symmetrical filters
- Low static power typically under 80mW and low dynamic power with 1.1 V core voltage
- Programmable IO support for LVCMOS 33/25/18/15/12, XGMII, LVTTL, LVDS, Bus-LVDS, 7:1 LVDS, LVPECL and MIPI D-PHY input interfaces