Lattice NXP PCIe Companion

Power-Efficient Edge Computing with i.MX 9 and Nexus FPGA

The NXP i.MX 9 application processor paired with a Lattice Nexus FPGA delivers a flexible, power-efficient platform for demanding embedded applications. Connected via PCIe, the two devices form a high-bandwidth, low-latency pipeline that offloads real-time processing, sensor aggregation, and protocol bridging from the main CPU — freeing the i.MX 9 for application-layer tasks.

Lattice Nexus FPGAs bring instant-on capability, deterministic I/O control, and field-updatable logic to the design, while the i.MX 9 contributes a powerful Arm Cortex-A55 core, rich multimedia support, and a robust Linux/RTOS ecosystem. Together, they address the needs of industrial automation, machine vision, communications infrastructure, and smart edge devices where adaptability and efficiency are non-negotiable.

This solution page covers reference architectures, PCIe interface guidelines, power budgets, and development resources to help you move from concept to production quickly.

Block Diagram

Lattice NXP PCIe Companion Block Diagram

Ordering Information

  1. ARW-CPNX-IMX95-Kit – suggested bundle OPN
    1. Bundle #1: LFCPNX-VERSA-EVN and IMX95LPD5EVK-19
  2. ARW-D2NX-IMX95-Kit-B – suggested bundle OPN
    1. Bundle #2: LFD2NX-VERSA-B-EVN and IMX95LPD5EVK-19

More Information

  1. Find more details on the NXP PCIe FPGA driver from this link: i.MX95 PCIe connection with FPGA - NXP Community
  2. For further details about this solution, please visit: Search – NXP Community

Documentation

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