Single Wire Signal Aggregation Demonstration

PCB Congestion Relief using FPGAs for Signal Aggregation and Transmission Over Single Wire

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This solution is an FPGA bitstream that can be used to configure a Lattice FPGA to perform as a Single-Wire aggregator for I2C, I2S, and GPIO signalling. No FPGA design is needed. Two configured devices (denoted as Master Single-Wire Aggregation Device and Slave Single-Wire Aggregation Device) can be used to aggregate and deaggregate multiple signals on a single physical wire through Time Domain Multiplexing (TDM)-based bidirectional communication. Note: UART can be implemented using GPIO channel. Single Wire Signal Aggregation Demonstration – Two boards are provided to demonstrate the complete working design in a stand-alone configuration.

Features

  • No FPGA tools knowledge necessary
  • Customizable via available Reference Design
  • Up to 7 channels can be aggregated
  • Supports ultra-low power devices
  • Multiple sets of ready-to-use configurations to support different use case applications are available

Jump to

Videos

How to Setup SWA Demo

如何设置单线聚合（SWA）演示

How to Run SWA Demo

如何运行单线聚合（SWA）演示

Video Thumbnail

Daisy-Chain Implementation of Single-Wire Signal Aggregation with Qualcomm RB5 Platform

Block Diagram

Single Wire Aggregation Demo/Dev Board – Block Diagram放大图片

单线聚合演示/开发板——框图

  • 可配置用于演示或原型设计
  • 提供12个测试开关
  • 跳线可将RD连接至数据生成器/验证器或者客户的原型设计
  • 12个输出LED

Ready-to-Use Device Configurations Demo

Single Wire Aggregation Demo / Development Board Configuration 1放大图片

配置#1 (I2Sx2_I2CSx1_I2CMx1_GPIOx8)

  • 两个定向I2S通道（32位数据宽度、36 kHz音频采样）
  • 一个I2C控制器到外设通道
  • 一个I2C外设到控制器通道
  • 6位双向GPIO通道
  • 2位双向GPIO通道
Single Wire Aggregation Demo / Development Board Configuration 2放大图片

配置#2 (I2CMx6_GPIOx6)

  • 六个I2C控制器到外设通道（400kHZ SCL时钟频率）
  • 6位双向GPIO通道
Single Wire Aggregation Demo / Development Board Configuration 3放大图片

配置#3 (I2CMx1_GPIOx12)

  • 一个I2C控制器到外设通道（1MHz SCL时钟频率）
  • 12位双向GPIO通道
Single Wire Aggregation Demo / Development Board Configuration 4放大图片

配置#4 (I2CMx3_I2CSx2_GPIOx15)

  • 三个I2C控制器到外设通道
  • 两个I2C外设到控制器通道
  • 15位控制器到外设GPIO通道
Single Wire Aggregation Demo / Development Board Configuration 5放大图片

配置#5 (I2Sx1_I2CMx1_I2CSx1_GPIOx8)

  • 1个定向I2S通道（32位数据宽度、最高48 kHz音频采样）
  • 一个I2C控制器到外设通道
  • 一个I2C外设到控制器通道
  • 6位双向GPIO通道
  • 2位双向GPIO通道

Documentation

快速参考
下载
标题 编号 版本 日期 格式 文件大小
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Single Wire Signal Aggregation User Guide
FPGA-UG-02117 1.1 5/1/2023 PDF 3.9 MB
标题 编号 版本 日期 格式 文件大小
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Single Wire Signal Aggregation Demonstration - Bitstream
9/7/2020 ZIP 334.4 KB

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