Solution:
To make Synplify Pro use EBR for the inferred ROM, use the attribute syn_romstyle with the value block_rom.
Synplify Pro infers ROM only when the address width is more than 3.
The usage of this attribute is the following:
Verilog Syntax
object /* syn_romstyle = "auto(default) | EBR | logic" */ ;
Verilog Example
reg [8:0] z /* synthesis syn_romstyle = "EBR" */;
VHDL Syntax
attribute syn_romstyle of object : object_type is "block_rom | logic" ;
VHDL Example
signal z : std_logic_vector(8 downto 0);
attribute syn_romstyle : string;
attribute syn_romstyle of z : signal is "logic";