LatticeECP3 supports CPRI (Common Public Radio Interface) low latency mode operation and the FIFO bridge in the SERDES/PCS is bypassed.
The conditions are that the operation runs at full synchronous mode and data is handed off from SerDes/PCS to FPGA fabric by the same system clock. To minimize latency variation factors, the FIFO bridge in the PCS is bypassed so that there is a fixed timing relationship between the PCS and FPGA fabric in the system. Thus, a low latency variation operation can be achieved.