ispClock 5620A Development Kit

The ispClock 5620 Development Kit includes everything the designer needs to quickly configure and evaluate the ispClock5620A on a fully assembled printed-circuit board. The four-layer board supports a 100-pin TQFP package, a header for user I/O and a JTAG programming cable connector. SMA connectors are installed to provide high-signal integrity access to selected high-speed I/O signals. JTAG programming signals can be generated by using an ispDOWNLOAD® programming cable connected between the evaluation board and a PC. All user-programmable features of the ispPAC-CLK5620A can be easily configured using Lattice Semiconductor's PAC-Designer® software.

Device Support

You will need the PAC-Designer software to use this board. PAC-Designer can be downloaded from the Lattice web site.

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Kit Contents

  • ispClock5620A Evaluation Board
  • ispDOWNLOAD Cable
  • AC Adapter
  • User Documentation

Board Photos

Top View

Click image to enlarge

Ordering Information

  • Ordering Part Number: PAC-SYSCLK5620AV
  • Click here to find an authorized Lattice distributor near you
  • Click here to order now from the Lattice Online Store

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
ispClock5620A Evaluation Board: ispPAC-CLK5620A-EV1
Describes the features and operation of the ispPAC-CLK5620A-EV1 evaluation board.
AN6072 3/1/2007 PDF 929.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
ispClock5620A Evaluation Board: ispPAC-CLK5620A-EV1
Describes the features and operation of the ispPAC-CLK5620A-EV1 evaluation board.
AN6072 3/1/2007 PDF 929.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Programming Cable User Guide
Describes the features and recommended usage guidelines of Lattice ispDOWNLOAD Cables.
FPGA-UG-02042 26.4 5/29/2020 PDF 1.4 MB

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