I3C Master IP Core

Control for I3C Bus Interface

The Lattice I3C IP Core is designed to comply with the MIPI I3C specification. Both Master and Slave versions of this IP Core are available.

The MIPI I3C interface eases sensor system design architectures in mobile wireless products by providing a fast, low-cost, low-power, two-wire digital interface for sensors. I3C a single scalable, cost effective, power efficient protocol to solve issues with the high protocol overhead, power consumption, nonstandard protocol, separate lines for interrupt and the rest requirement. Implementing the I3C Specification greatly increases the implementation flexibility for an ever-expanding sensor subsystem as efficiently and at as low cost as possible.

I3C is backward compatible with many Legacy I2C Devices, but I3C offers greater than 10x speed improvements, more efficient bus power management, new communication Modes, and new Device roles, including an ability to change Device Roles over time (i.e., the initial Master can cooperatively pass the Mastership to another I3C Device on the Bus, if the requesting I3C Device supports Secondary Master feature).


  • Two wire serial interface up to 12.5 MHz using Push-Pull
  • Legacy I2C Device co-existence on the same Bus (with some limitations)
  • Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
  • I2C-like SDR and HDR-DDR messaging
  • Multi-Master capability
  • In-Band Interrupt and Hot-join support

Block Diagram

Ordering Information

Family Part Numbers Description
CertusPro-NX I3C-M-CPNX-U Single-Design License
CertusPro-NX I3C-M-CPNX-UT Multi-Site License
Certus-NX I3C-M-CTNX-U Single-Design License
Certus-NX I3C-M-CTNX-UT Multi-Site License
CrossLink-NX I3C-M-CNX-U Single-Design License
CrossLink-NX I3C-M-CNX-UT Multi-Site License


Quick Reference
I3C Master IP Core 2.0 - Lattice Radiant Software
FPGA-IPUG-02128 1.1 6/23/2021 PDF 1.3 MB
I3C Master IP Core - Lattice Radiant Software
FPGA-IPUG-02082 1.2 6/24/2020 PDF 1.6 MB

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