DF6805: 8-bit FAST Microcontrollers Family

DCD LogoThe DF6805 is a advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. DF6805 soft core is binary-compatible with the industry standard 68HC05 8-bit microcontroller and can achieve a performance 45-100 million instructions per second. There are two configurations of DF6805: Harvard where data and program buses are separated, and von Neumann with common program and data bus DF6805 has FAST architecture that is 4.1 times faster compared to original implementation. Core in standard configuration has integrated on chip major peripheral function.

The DF6805 Microcontroller Core contains full-duplex UART (Asynchronous serial communications interface (SCI), and can also be equipped with the Synchronous Serial Peripheral Interface SPI.

The main 16-bit, free-running timer system has implemented two input capture lines and two output-compare lines.

Self-monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a nonmaskable interrupt if illegal opcode is detected.

Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the DF6805 IP Core especially attractive for automotive and battery-driven applications.

DF6805 is fully customizable, which means it is delivered in the exact configuration to meet users requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.


  • FAST architecture, 4.1 times faster than the original implementation
  • Software compatible with industry standard 68HC05
  • Configurable Harvard or Von Neumann architectures
  • 64 bytes of System Function Registers space (SFRs)
  • Up to 64k bytes of Program Memory
  • Up to 64k bytes of Data Memory
  • De-multiplexed Address/Data Bus to allow easy connection to memory
  • Two power saving modes: STOP, WAI
  • Ready pin allows Core to operate with slow program and data memories
  • Fully synthesizable, static synchronous design with no internal tri-states
  • No internal reset generator or gated clock
  • Scan test ready
  • Technology independent HDL source code
  • Core can be fully customized
  • 1 GHz virtual clock frequency compared to original implementation

Jump to

Block Diagram

Performance and Size

Device Speed grade Fmax LUTs PFUs
XP -5 46 MHz 2081 538
ECP -5 51 MHz 2081 538
EC -5 51 MHz 2081 538
ORCA 4 -3 30 MHz 1565 296

Ordering Information

This IP core is supported and sold by DCD, contact DCD at support@dcd.pl or visit their website at www.dcd.pl for more information.