My top level design and testbench are in VHDL but some of my lower level modules are in Verilog. How do I perform mixed language simulation with Aldec generally?
For Aldec's Active-HDL, Lattice provides pre-compiled libraries for both, Verilog and VHDL. All the libraries starting with the name \u201Covi_\u201D are pre-compiled Verilog libraries and the libraries starting without \u201Covi_\u201D are equivalent pre-compiled VHDL libraries. As an example, \u201Covi_ecp3" is for the LatticeECP3 Verilog library and "ecp3" is for the LatticeECP3 VHDL library. For the mixed language simulation, we recommend that the user add \u201C-L ovi_ecp2m\u201D and \u201C-L ecp2m\u201D to the vsim command. If this is not done, users may encounter errors about "unresolved hierarchical references".