Simulation and hardware show that registers are clocked with a fast clock in the design, while they are supposed to be clocked by a slow clock.
This usually happens when the slow clock used for the registers is generated from a fast clock. The synthesis tool by default converts the generated clock (slow clock) into clock enable for the registers, and uses the original clock (fast clock) to clock the register.
Most of the time it works well and preserves the functionality of the design when the slow clock is directly derived from the fast clock. It could cause problem when the slow clock is controlled by other signals in additional to the fast clock, and these signals are not clocked by the fast clock.
Users have the choice to stop the synthesis tool to convert the generated clock into clock enable. Follow the steps to disable the feature in the ispLEVER Project Navigator GUI:
- Highlight the source file
- On the right hand side you'll see Synplify Synthesis Verilog File, highlight it and right click on it, you'll see Properties.
- Click on Properties, and scroll down to Fixed Generated Clocks. Enter 0 to replace default value 3 to disable this function
- Rerun synthesis and the entire software flow to see the change in the design behavior