Aptina HiSPi to Parallel Sensor Bridge

Reference Design LogoTo support higher bandwidth sensors, Aptina Imaging has introduced a high-speed serial interface called HiSPi. The HiSPi interface can operate from one to four lanes of serial data, plus one clock lane. Each signal is differential and can run at speeds up to 700 Mbps. To interface to an ISP with a traditional parallel bus, Lattice has created a bridge from HiSPi to a parallel format. The LatticeXP2™-5 or LatticeMachXO2-1200 non-volatile FPGA provides an efficient and cost-effective solution for HiSPi-to-parallel bridging.


  • Complete Reference Design
  • Supports HiSPi formats Packetized-SP, Streaming-SP, Streaming-S or ActiveStart-SP8
    • From one to four lanes, running at up to 700 Mbps each
  • Either HDR or Linear Mode supported
  • Designed to Emulate Parallel Sensor Output
    • Output bus widths of 10, 12, 14 or 16 bits
  • Bridge Device Offered in Space-saving 8x8 mm 132csBGA. TQFP Packages Also Available
  • Requires No External PROM
  • Tested with TI TMS320DM8127, TMS320DM36X and TMS320DM385 ISPs
  • Tested with Aptina MT9M034, MT9M024, AR331, AR330 & MT9J003 Sensors
  • Parallel Interface can be Configured for 1.8V, 2.5V or 3.3V LVCMOS Levels
  • The Lattice XO2-1200 and XP2-5 are available in commercial or industrial temperature grades
  • The Lattice XP2-5 is AEC-Q100 automotive qualified temperature range

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